Datasheet Texas Instruments PADS5546IRGZT

ManufacturerTexas Instruments
SeriesADS5546
Part NumberPADS5546IRGZT
Datasheet Texas Instruments PADS5546IRGZT

14-Bit, 190-MSPS Analog-to-Digital Converter (ADC) 48-VQFN -40 to 85

Datasheets

14-Bits 190 MSPS ADC With DDR LVDS/CMOS Outputs datasheet
PDF, 2.1 Mb, Revision: D, File published: May 7, 2007
Extract from the document

Prices

Status

Lifecycle StatusPreview (Device has been announced but is not in production. Samples may or may not be available)
Manufacture's Sample AvailabilityNo

Packaging

Pin48
Package TypeRGZ
Industry STD TermVQFN
JEDEC CodeS-PQFP-N
Width (mm)7
Length (mm)7
Thickness (mm).9
Pitch (mm).5
Max Height (mm)1
Mechanical DataDownload

Parametrics

# Input Channels1
Analog Input BW(MHz)500
Approx. Price (US$)116.49 | 100u
ArchitecturePipeline
DNL(Max)(+/-LSB)0.5
DNL(Typ)(+/-LSB)0.5
ENOB(Bits)11.8
INL(Max)(+/-LSB)3
INL(Typ)(+/-LSB)3
Input BufferNo
Input Range(Vp-p)2
InterfaceParallel CMOS
Parallel LVDS
Operating Temperature Range(C)-40 to 85
Package GroupVQFN
Package Size: mm2:W x L (PKG)48VQFN: 49 mm2: 7 x 7(VQFN)
Power Consumption(Typ)(mW)1130
RatingCatalog
Reference ModeExt
Int
Resolution(Bits)14
SFDR(dB)87
SINAD(dB)72.8
SNR(dB)73.5
Sample Rate(Max)(MSPS)190

Eco Plan

RoHSNot Compliant
Pb FreeNo

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Application Notes

  • QFN Layout Guidelines
    PDF, 1.3 Mb, File published: Jul 28, 2006
    Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs.
  • CDCE62005 as Clock Solution for High-Speed ADCs
    PDF, 805 Kb, File published: Sep 4, 2008
    TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, File published: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, File published: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, File published: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

Model Line

Series: ADS5546 (2)

Manufacturer's Classification

  • Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)
EMS supplier