Datasheet Texas Instruments SN74F112DRE4
| Manufacturer | Texas Instruments |
| Series | SN74F112 |
| Part Number | SN74F112DRE4 |
Dual J-K Negative-Edge-Triggered Flip-Flop With Clear And Preset 16-SOIC 0 to 70
Datasheets
Dual Negative-Edge-Triggered J-K Flip-Flop With Clear And Preset datasheet
PDF, 639 Kb, Revision: A, File published: Oct 1, 1993
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 16 |
| Package Type | D |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2500 |
| Carrier | LARGE T&R |
| Device Marking | F112 |
| Width (mm) | 3.91 |
| Length (mm) | 9.9 |
| Thickness (mm) | 1.58 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 1.75 |
| Mechanical Data | Download |
Parametrics
| Bits | 2 |
| F @ Nom Voltage(Max) | 70 Mhz |
| ICC @ Nom Voltage(Max) | 19 mA |
| Output Drive (IOL/IOH)(Max) | -1/20 mA |
| Package Group | SOIC |
| Package Size: mm2:W x L | 16SOIC: 59 mm2: 6 x 9.9(SOIC) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | F |
| VCC(Max) | 5.5 V |
| VCC(Min) | 4.5 V |
| Voltage(Nom) | 5 V |
| tpd @ Nom Voltage(Max) | 7.5 ns |
Eco Plan
| RoHS | Compliant |
Model Line
Series: SN74F112 (9)
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop
