Datasheet Texas Instruments DAC121S101QML-SP
| Manufacturer | Texas Instruments |
| Series | DAC121S101QML-SP |
12-Bit Micro Power Digital-to-Analog Converter with Rail-to-Rail Output
Datasheets
DAC121S101QML-SP Radiation Hardened 12-Bit Micro Power Digital-to-Analog Converter With Rail-to-Rail Output datasheet
PDF, 887 Kb, Revision: F, File published: Jul 29, 2016
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Prices
Status
| 5962R0722601VZA | 5962R0722602VZA | DAC121S101 MDR | DAC121S101WGMPR | DAC121S101WGRLV | DAC121S101WGRQV | |
|---|---|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No | No | No | No | No |
Packaging
| 5962R0722601VZA | 5962R0722602VZA | DAC121S101 MDR | DAC121S101WGMPR | DAC121S101WGRLV | DAC121S101WGRQV | |
|---|---|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 | 5 | 6 |
| Pin | 10 | 10 | 10 | 10 | 10 | |
| Package Type | NAC | NAC | Y | NAC | NAC | NAC |
| Industry STD Term | CFP | CFP | CFP | CFP | CFP | |
| JEDEC Code | R-CDFP-G | R-CDFP-G | R-CDFP-G | R-CDFP-G | R-CDFP-G | |
| Package QTY | 54 | 54 | 10 | 54 | 54 | 54 |
| Device Marking | DAC121S101 | 02VZA ACO | ACO | WGRLV Q | 01VZA ACO | |
| Width (mm) | 6.121 | 6.121 | 6.121 | 6.121 | 6.121 | |
| Length (mm) | 6.858 | 6.858 | 6.858 | 6.858 | 6.858 | |
| Thickness (mm) | 1.778 | 1.778 | 1.778 | 1.778 | 1.778 | |
| Pitch (mm) | 1.27 | 1.27 | 1.27 | 1.27 | 1.27 | |
| Max Height (mm) | 2.34 | 2.34 | 2.34 | 2.34 | 2.34 | |
| Mechanical Data | Download | Download | Download | Download | Download |
Parametrics
| Parameters / Models | 5962R0722601VZA | 5962R0722602VZA | DAC121S101 MDR | DAC121S101WGMPR | DAC121S101WGRLV | DAC121S101WGRQV |
|---|---|---|---|---|---|---|
| Architecture | String | String | String | String | String | String |
| DAC Channels | 1 | 1 | 1 | 1 | 1 | 1 |
| DNL(Max), +/-LSB | 1 | 1 | 1 | 1 | 1 | 1 |
| Gain Error(Max), %FSR | 1 | 1 | 1 | 1 | 1 | 1 |
| INL(Max), +/-LSB | 8 | 8 | 8 | 8 | 8 | 8 |
| Interface | SPI | SPI | SPI | SPI | SPI | SPI |
| Operating Temperature Range, C | -55 to 125,25 | -55 to 125,25 | -55 to 125,25 | -55 to 125,25 | -55 to 125,25 | -55 to 125,25 |
| Output Range Max., mA | 5.5 | 5.5 | 5.5 | 5.5 | 5.5 | 5.5 |
| Output Type | Buffered Voltage | Buffered Voltage | Buffered Voltage | Buffered Voltage | Buffered Voltage | Buffered Voltage |
| Package Group | CFP | CFP | CFP | CFP | CFP | CFP |
| Package Size: mm2:W x L, PKG | See datasheet (CFP) | See datasheet (CFP) | See datasheet (CFP) | See datasheet (CFP) | See datasheet (CFP) | See datasheet (CFP) |
| Power Consumption(Typ), mW | 0.52 | 0.52 | 0.52 | 0.52 | 0.52 | 0.52 |
| Rating | Space | Space | Space | Space | Space | Space |
| Reference: Type | Ext | Ext | Ext | Ext | Ext | Ext |
| Resolution, Bits | 12 | 12 | 12 | 12 | 12 | 12 |
| Sample / Update Rate, MSPS | 1.8 | 1.8 | 1.8 | 1.8 | 1.8 | 1.8 |
| Settling Time, µs | 12.5 | 12.5 | 12.5 | 12.5 | 12.5 | 12.5 |
Eco Plan
| 5962R0722601VZA | 5962R0722602VZA | DAC121S101 MDR | DAC121S101WGMPR | DAC121S101WGRLV | DAC121S101WGRQV | |
|---|---|---|---|---|---|---|
| RoHS | See ti.com | See ti.com | Compliant | See ti.com | See ti.com | See ti.com |
Application Notes
- AN-2001 Daisy Chaining Precision DACs (Rev. A)PDF, 75 Kb, Revision: A, File published: May 1, 2013
It is not uncommon for the system designer to face a quagmire of reconciling the system complexity withthe desire to keep the system footprint small. One specific example that often arises in the context ofsmall system footprint is the need for single master controller to communicate with a number of slavedevices. This is not much of a problem if the master controller has multiple I/O resour
Model Line
Series: DAC121S101QML-SP (6)
Manufacturer's Classification
- Semiconductors> Space & High Reliability> Data Converter> Digital to Analog Converters
