Datasheet Texas Instruments TLC5510IPW
| Manufacturer | Texas Instruments |
| Series | TLC5510 |
| Part Number | TLC5510IPW |
8-Bit, 20-MSPS Analog-to-Digital Converter (ADC) 24-TSSOP -20 to 75
Datasheets
8-Bit High-Speed Analog-to-Digital Converters datasheet
PDF, 892 Kb, Revision: L, File published: Jun 11, 2003
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 24 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 60 |
| Carrier | TUBE |
| Device Marking | Y5510 |
| Width (mm) | 4.4 |
| Length (mm) | 7.8 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| # Input Channels | 1 |
| Analog Input BW | 14 MHz |
| Architecture | Flash |
| DNL(Max) | 0.75 +/-LSB |
| DNL(Typ) | 0.3 +/-LSB |
| ENOB | 6.8 Bits |
| INL(Max) | 1 +/-LSB |
| INL(Typ) | 0.4 +/-LSB |
| Input Buffer | No |
| Input Range | 2 Vp-p |
| Interface | Parallel CMOS |
| Operating Temperature Range | -20 to 75 C |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) PKG |
| Power Consumption(Typ) | 127.5 mW |
| Rating | Catalog |
| Reference Mode | Ext |
| Resolution | 8 Bits |
| SFDR | 42 dB |
| SINAD | 44 dB |
| SNR | 46 dB |
| Sample Rate(Max) | 20 MSPS |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- Interfacing the TLC5510 Analog-to-Digital Converter to the TMS320C203 DSPPDF, 401 Kb, File published: Apr 27, 2000
This application report is a summary of the application note titled Interfacing the TLC5510 Analog-to-Digital Converter to the TMS320C203 DSP (literature number SLAA029) that presents guidelines for interfacing the TI TLC5510 analog-to-digital converter (ADC) to the TI TMS320C203 DSP. The TLC5510 is a CMOS, 8-bit, 20 MSPS (megasamples per second) ADC utilizing a semi-flash architecture. The TLC551 - Interfacing the TLC5510 Analog-to-Digital Converter to the TMS320C203 DSPPDF, 540 Kb, File published: Feb 1, 1998
This application report presents guidelines for interfacing the Texas Instruments (TI(TM)) TLC5510 8-bit parallel-output analog-to-digital converter (ADC) to the TI TMS320C203 DSP data bus. The 8-bit ADC operates at a rate of 20 MHz. The C callable application program (assembly code) used to initialize the TMS320C203 and execute the code is also discussed.This report serves as reference inform - Interfacing A/D Converters TLC5540/10 to the DSKplus DSP Starter Kit TMS320C54xPDF, 206 Kb, File published: Apr 1, 1997
This Application Note describes the construction of a test circuit using the A/D converters TLC5540 and TLC5510, and alternative ways of interfacing these converters to the DSKplus DSP starter kit TMS320C54x. Details are given of the test circuit of the TLC5540/10 and of the interface, and the programming of the digital signal processor TMS320C54x is also described. - CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, File published: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, File published: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
Model Line
Series: TLC5510 (5)
- TLC5510INS TLC5510INSLE TLC5510INSR TLC5510IPW TLC5510IPWR
Manufacturer's Classification
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)
