Datasheet Texas Instruments ADS58C48IPFPR
| Manufacturer | Texas Instruments |
| Series | ADS58C48 |
| Part Number | ADS58C48IPFPR |
Quad-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter (ADC) 80-HTQFP -40 to 85
Datasheets
Quad Channel IF Receiver with SNRBoost 3G datasheet
PDF, 2.7 Mb, File published: May 27, 2010
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Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 80 |
| Package Type | PFP |
| Industry STD Term | HTQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | ADS58C48I |
| Width (mm) | 12 |
| Length (mm) | 12 |
| Thickness (mm) | 1 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| # Input Channels | 4 |
| Analog Input BW | 600 MHz |
| Architecture | Pipeline |
| DNL(Max) | 1.2 +/-LSB |
| ENOB | 10.7 Bits |
| INL(Max) | 2 +/-LSB |
| INL(Typ) | 1 +/-LSB |
| Input Buffer | No |
| Input Range | 2 Vp-p |
| Interface | Parallel CMOS,Parallel LVDS |
| Operating Temperature Range | -40 to 85 C |
| Package Group | HTQFP |
| Package Size: mm2:W x L | 80HTQFP: 196 mm2: 14 x 14(HTQFP) PKG |
| Power Consumption(Typ) | 900 mW |
| Rating | Catalog |
| Reference Mode | Int |
| Resolution | 11 Bits |
| SFDR | 84 dB |
| SINAD | 66.6 dB |
| SNR | 66.6 dB |
| Sample Rate(Max) | 200 MSPS |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: ADS58C28EVM
ADS58C28 Dual-Channel, 11-Bit, 200-MSPS Analog-to-Digital Converter Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: TSW2170EVM
TSW2170 Crystal Filtered 70MHz Source Evaluation Module
Lifecycle Status: Active (Recommended for new designs) - Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- Using Windowing With SNRBoost 3G TechnologyPDF, 498 Kb, File published: Aug 30, 2010
Coherency is a well-known requirement when using FFT techniques to examine the spectrum of the output of an analog-to-digital converter. SNRBoost(3G) technology results in loss in coherency, and this can be seen as an unstable noise floor in the spectrum. Windowing of the ADC output is a well-known solution to restore coherency and stable spectrum.However, windowing also modifies the amplitude o - Understanding Low-Amplitude Behavior of 11-bit ADCsPDF, 678 Kb, File published: Oct 22, 2011
In TI’s line of high-speed analog-to-digital converters (ADCs) with SNRBoost technology, output amplitude tends to deviate from its expected value when the applied input amplitude is small. This application note explains this phenomenon and the reasons it occurs. - Power Supply Design for the ADS41xx (Rev. A)PDF, 401 Kb, Revision: A, File published: Dec 29, 2011
System designers traditionally power the high-speed data converter in their systems from a low-noise, low-dropout linear regulator (LDO) in order to achieve the performance described in the analog-to-digital converter (ADC) data sheet. However, LDOs inherently are not very power efficient. Switching regulators, on the other hand, offer good power efficiency but typically come with higher output no - High-Speed Analog-to-Digital Converter BasicsPDF, 1.1 Mb, File published: Jan 11, 2012
The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil - Band-Pass Filter Design Techniques for High-Speed ADCsPDF, 733 Kb, File published: Feb 27, 2012
Several well-known methods exist for designing passive inductor-capacitor (LC) filters with resistive load terminations. However, when LC filters are used to drive the analog input pins of a high-speed analog-to-digital converter (ADC), special consideration must be given to the ADC input impedance. Not accounting for the ADC input impedance often results in a filter design that does not meet the - CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, File published: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, File published: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, File published: May 18, 2015
Model Line
Series: ADS58C48 (2)
- ADS58C48IPFP ADS58C48IPFPR
Manufacturer's Classification
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)
