Datasheet Texas Instruments DAC5682ZIRGCT

Manufacturer	Texas Instruments
Series	DAC5682Z
Part Number	DAC5682ZIRGCT

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Design Kits & Evaluation Modules

• Evaluation Modules & Boards: FMC-DAC-ADAPTER
  High Speed DAC to FMC (Xilinx) Header Adapter Card
  Lifecycle Status: Active (Recommended for new designs)
  
• Evaluation Modules & Boards: DAC5681EVM
  DAC5681 16-Bit, 1.0-GSPS Digital-to-Analog Converter Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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• Evaluation Modules & Boards: DAC5681ZEVM
  DAC5681Z 16-Bit, 1.0-GSPS, 1x-4x Interpolating Digital-to-Analog Converter Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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• Evaluation Modules & Boards: TRF3703-17EVM
  TRF3703-17 Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
• Evaluation Modules & Boards: DAC5682ZEVM
  DAC5682Z Dual-Channel, 16-Bit, 1.0-GSPS Digital-to-Analog Converter Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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• Evaluation Modules & Boards: TSW3100EVM
  TSW3100 Pattern Generator Module
  Lifecycle Status: Obsolete (Manufacturer has discontinued the production of the device)
  
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• Evaluation Modules & Boards: TSW2200EVM
  TSW2200 Low-Cost Portable Power Supply Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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Application Notes

• Download
  Design of Differential Filters for High-Speed Signal Chains (Rev. B)
  PDF, 166 Kb, Revision: B, File published: Apr 30, 2010
  Differential filters have many desirable attributes. The task of designing differential filters can seem daunting at first. Single-ended filters designed in any filter design package can be converted to a differential implementation. This application report explores simple conversion techniques for low-pass, high-pass, and band-pass LC filters.
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  Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs
  PDF, 319 Kb, File published: Jul 14, 2009
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  Passive Terminations for Current Output DACs
  PDF, 244 Kb, File published: Nov 10, 2008
  The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
• Download
  Q3 2009 Issue Analog Applications Journal
  PDF, 2.1 Mb, File published: Jul 14, 2009
• Download
  High Speed Digital-to-Analog Converters Basics (Rev. A)
  PDF, 829 Kb, Revision: A, File published: Oct 23, 2012
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  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, File published: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, File published: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

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Manufacturer's Classification

• Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)