Datasheet Texas Instruments DAC5686IPZPG4
| Manufacturer | Texas Instruments |
| Series | DAC5686 |
| Part Number | DAC5686IPZPG4 |
Dual-Channel, 16-Bit, 500-MSPS, 1x-16x Interpolating Digital-to-Analog Converter (DAC) 100-HTQFP -40 to 85
Datasheets
16-Bit 500 MSPS 2x-16x Interpolating Dual-Channel DAC datasheet
PDF, 861 Kb, Revision: F, File published: Jun 3, 2009
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 100 |
| Package Type | PZP |
| Industry STD Term | HTQFP |
| JEDEC Code | S-PQFP-G |
| Package QTY | 90 |
| Carrier | EIAJ TRAY (10+1) |
| Device Marking | DAC5686IPZP |
| Width (mm) | 14 |
| Length (mm) | 14 |
| Thickness (mm) | 1 |
| Pitch (mm) | .5 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| Architecture | Current Sink |
| DAC Channels | 2 |
| Interface | Parallel CMOS |
| Interpolation | 1x,2x,4x,8x,16x |
| Operating Temperature Range | -40 to 85 C |
| Package Group | HTQFP |
| Package Size: mm2:W x L | 100HTQFP: 256 mm2: 16 x 16(HTQFP) PKG |
| Power Consumption(Typ) | 445 mW |
| Rating | Catalog |
| Resolution | 16 Bits |
| SFDR | 72 dB |
| Sample / Update Rate | 500 MSPS |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: TSW3100EVM
TSW3100 Pattern Generator Module
Lifecycle Status: Obsolete (Manufacturer has discontinued the production of the device) - Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- DAC5686/DAC5687 Clock Generation Using PLL & External Clock Modes (Rev. A)PDF, 686 Kb, Revision: A, File published: Jul 21, 2005
DAC5686/DAC5687 Application NOte Clock Generation Using PLL & External Clock Modes - Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACsPDF, 319 Kb, File published: Jul 14, 2009
- Passive Terminations for Current Output DACsPDF, 244 Kb, File published: Nov 10, 2008
The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance - Q3 2009 Issue Analog Applications JournalPDF, 2.1 Mb, File published: Jul 14, 2009
- High Speed Digital-to-Analog Converters Basics (Rev. A)PDF, 829 Kb, Revision: A, File published: Oct 23, 2012
- Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
Model Line
Series: DAC5686 (2)
- DAC5686IPZP DAC5686IPZPG4
Manufacturer's Classification
- Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)
