16-bit, 200 MSPS ADC with buffered inputs 64-VQFN -40 to 85
PDF, 275 Kb, File published: Jan 11, 2011
ADS5493, ADS5400, ADS5481, ADS5482, ADS5483, ADS5484, ADS5485 Input Impedance Measurement Using ADC FFT Data
PDF, 1.1 Mb, File published: Jan 11, 2012
The goal of this document is to introduce a wide range of theories and topics that are relevant to high-speed, analog-to-digital converters (ADC). This document provides details on sampling theory,
PDF, 1.3 Mb, File published: Jul 28, 2006
Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and bet
PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
ADS6129, ADS6149 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat
PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
ADS4149 Why Use Oversampling when Undersampling Can Do the Job?
PDF, 376 Kb, File published: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs
PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies
PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the refe
PDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of
PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
AB-082 Principles of Data Acquisition and Conversion
PDF, 64 Kb, File published: Oct 2, 2000
It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration s
PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (ΔΣ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specificati
PDF, 69 Kb, Revision: A, File published: May 18, 2015
AB-084 Analog-to-Digital Grounding Practices Affect System Performance
PDF, 95 Kb, File published: Oct 2, 2000
Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its oper