Datasheet Texas Instruments ADS7230IPWG4
| Manufacturer | Texas Instruments |
| Series | ADS7230 |
| Part Number | ADS7230IPWG4 |
Low-Power, 12-Bit, 1-MHz, Single/Dual Unipolar Input, ADCs with Serial Interface 16-TSSOP -40 to 85
Datasheets
LOW-POWER, 12-BIT, 1MHz, SINGLE/DUAL UNIPOLAR INPUT, ADC w/SERIAL INTERFACE datasheet
PDF, 1.5 Mb, Revision: A, File published: Jun 18, 2009
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Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 16 | 16 |
| Package Type | PW | PW |
| Industry STD Term | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G |
| Package QTY | 90 | 90 |
| Carrier | TUBE | TUBE |
| Device Marking | ADS | 7230I A |
| Width (mm) | 4.4 | 4.4 |
| Length (mm) | 5 | 5 |
| Thickness (mm) | 1 | 1 |
| Pitch (mm) | .65 | .65 |
| Max Height (mm) | 1.2 | 1.2 |
| Mechanical Data | Download | Download |
Parametrics
| # Input Channels | 2 |
| Analog Voltage AVDD(Max) | 5.5 V |
| Analog Voltage AVDD(Min) | 2.7 V |
| Architecture | SAR |
| Digital Supply(Max) | 5.5 V |
| Digital Supply(Min) | 1.65 V |
| INL(Max) | 0.5 +/-LSB |
| Input Range(Max) | 5.5 V |
| Input Type | Pseudo-Differential,Single-Ended |
| Integrated Features | Daisy-Chainable,Oscillator |
| Interface | Serial |
| Multi-Channel Configuration | Multiplexed |
| Operating Temperature Range | -40 to 85 C |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 16TSSOP: 32 mm2: 6.4 x 5(TSSOP) PKG |
| Power Consumption(Typ) | 13.7 mW |
| Rating | Catalog |
| Reference Mode | Ext |
| Resolution | 12 Bits |
| SINAD | 73.7 dB |
| SNR | 73.9 dB |
| Sample Rate (max) | 1MSPS SPS |
| Sample Rate(Max) | 1 MSPS |
| THD(Typ) | -88.5 dB |
Eco Plan
| RoHS | Compliant |
Application Notes
- Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, Revision: A, File published: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, File published: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, File published: May 18, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
Model Line
Series: ADS7230 (5)
- ADS7230IPW ADS7230IPWG4 ADS7230IPWR ADS7230IRSAR ADS7230IRSAT
Manufacturer's Classification
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)
