Datasheet Texas Instruments SN74LVTH273DBLE
| Manufacturer | Texas Instruments |
| Series | SN74LVTH273 |
| Part Number | SN74LVTH273DBLE |
3.3-V ABT Octal D-Type Flip-Flops With Clear 20-SSOP -40 to 85
Datasheets
SN54LVTH273, SN74LVTH273 datasheet
PDF, 1.2 Mb, Revision: M, File published: Oct 13, 2003
Extract from the document
Prices
Status
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 20 |
| Package Type | DB |
| Industry STD Term | SSOP |
| JEDEC Code | R-PDSO-G |
| Width (mm) | 5.3 |
| Length (mm) | 7.2 |
| Thickness (mm) | 1.95 |
| Pitch (mm) | .65 |
| Max Height (mm) | 2 |
| Mechanical Data | Download |
Parametrics
| 3-State Output | No |
| Approx. Price (US$) | 0.26 | 1ku |
| Bits(#) | 8 |
| F @ Nom Voltage(Max)(Mhz) | 160 |
| ICC @ Nom Voltage(Max)(mA) | 5 |
| Input Type | TTL |
| Operating Temperature Range(C) | -40 to 85 |
| Output Drive (IOL/IOH)(Max)(mA) | 64/-32 |
| Output Type | TTL |
| Package Group | SSOP |
| Package Size: mm2:W x L (PKG) | 20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP) |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | LVT |
| VCC(Max)(V) | 3.6 |
| VCC(Min)(V) | 2.7 |
| Voltage(Nom)(V) | 3.3 |
| tpd @ Nom Voltage(Max)(ns) | 4.9 |
Eco Plan
| RoHS | Not Compliant |
| Pb Free | No |
Application Notes
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, File published: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed. - Bus-Hold CircuitPDF, 418 Kb, File published: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
Model Line
Series: SN74LVTH273 (16)
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Flip-Flop
