Datasheet Texas Instruments THS1041CPWR
| Manufacturer | Texas Instruments |
| Series | THS1041 |
| Part Number | THS1041CPWR |
10-Bit, 40-MSPS Analog-to-Digital Converter (ADC) 28-TSSOP 0 to 70
Datasheets
10-Bit, 40-MSPS Analog-to-Digital Converter With PGA and Clamp datasheet
PDF, 951 Kb, Revision: C, File published: Oct 28, 2004
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 28 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | TH1041 |
| Width (mm) | 4.4 |
| Length (mm) | 9.7 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| # Input Channels | 1 |
| Analog Input BW | 900 MHz |
| Architecture | Pipeline |
| DNL(Max) | 1 +/-LSB |
| DNL(Typ) | 0.3 +/-LSB |
| ENOB | 9.5 Bits |
| INL(Max) | 1.5 +/-LSB |
| INL(Typ) | 0.75 +/-LSB |
| Input Buffer | No |
| Input Range | 2 Vp-p |
| Interface | Parallel CMOS |
| Operating Temperature Range | 0 to 70 C |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP) PKG |
| Power Consumption(Typ) | 103 mW |
| Rating | Catalog |
| Reference Mode | Ext,Int |
| Resolution | 10 Bits |
| SFDR | 70 dB |
| SINAD | 60 dB |
| SNR | 57 dB |
| Sample Rate(Max) | 40 MSPS |
Eco Plan
| RoHS | Compliant |
Design Kits & Evaluation Modules
- Evaluation Modules & Boards: TSW2200EVM
TSW2200 Low-Cost Portable Power Supply Evaluation Module
Lifecycle Status: Active (Recommended for new designs)
Application Notes
- Clamp function of high-speed ADC THS1041PDF, 235 Kb, File published: Oct 10, 2006
- High-Speed ADC THS1041and FPGA Interface ConsiderationsPDF, 130 Kb, File published: Mar 15, 2007
The Texas Instruments THS1041 is a 10-bit, 40-MSPS, high-speed analog-to-digital converter (ADC). For many years because of its low power dissipation and extended life, it has been used in various applications such as programmable gain amplifier and built-in clamp. With recent FPGA development, some application systems have been upgraded with a direct interface of the THS1041 to an FPGA, for examp - CDCE62005 as Clock Solution for High-Speed ADCsPDF, 805 Kb, File published: Sep 4, 2008
TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, File published: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Noise Analysis for High Speed Op Amps (Rev. A)PDF, 256 Kb, Revision: A, File published: Jan 17, 2005
As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu
Model Line
Series: THS1041 (8)
Manufacturer's Classification
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > High Speed ADCs (>10MSPS)
