Datasheet Texas Instruments ADS7865IPBSG4

Manufacturer	Texas Instruments
Series	ADS7865
Part Number	ADS7865IPBSG4

Dual, 2MSPS, 12-Bit, 3+3 or 2+2 Channel, Simultaneous Sampling ADC 32-TQFP -40 to 125

Datasheets

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PDF, 780 Kb, Revision: C, File published: Apr 17, 2012

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Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Packaging

Pin	32
Package Type	PBS
Industry STD Term	TQFP
JEDEC Code	S-PQFP-G
Package QTY	250
Carrier	JEDEC TRAY (5+1)
Device Marking	7865I A
Width (mm)	5
Length (mm)	5
Thickness (mm)	1
Pitch (mm)	.5
Max Height (mm)	1.2
Mechanical Data	Download

Parametrics

# Input Channels	6
Analog Voltage AVDD(Max)	5.5 V
Analog Voltage AVDD(Min)	2.7 V
Architecture	SAR
Digital Supply(Max)	5.5 V
Digital Supply(Min)	2.7 V
INL(Max)	1 +/-LSB
Input Range(Max)	5.5 V
Input Type	Differential,Pseudo-Differential
Integrated Features	N/A
Interface	Parallel
Multi-Channel Configuration	Multiplexed
Operating Temperature Range	-40 to 125 C
Package Group	TQFP
Package Size: mm2:W x L	32TQFP: 49 mm2: 7 x 7(TQFP) PKG
Power Consumption(Typ)	30 mW
Rating	Catalog
Reference Mode	Ext,Int
Resolution	12 Bits
SINAD	71.3 dB
SNR	71.7 dB
Sample Rate (max)	2MSPS SPS
Sample Rate(Max)	2 MSPS
THD(Typ)	-87 dB

Eco Plan

RoHS

Compliant

Application Notes

Download
Interfacing the ADS786x to the MSP430F2013
PDF, 90 Kb, File published: Jun 15, 2006
This application report presents methods of interfacing the ADS7866/67/68 12/10/8-bit SAR analog-to-digital converter to the MSP430F2013 universal serial interface (USI) in SPI mode. The flexible clocking scheme of the USI port, along with the internal 16-bit shift register, provides an easy hardware/software interface to this series of high-speed, micro-power SAR converters.
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Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)
PDF, 227 Kb, Revision: A, File published: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different
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Determining Minimum Acquisition Times for SAR ADCs, part 2
PDF, 215 Kb, File published: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
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Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
PDF, 69 Kb, Revision: A, File published: May 18, 2015
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A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
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Principles of Data Acquisition and Conversion (Rev. A)
PDF, 132 Kb, Revision: A, File published: Apr 16, 2015

Model Line

Series: ADS7865 (3)

ADS7865IPBS ADS7865IPBSG4 ADS7865IPBSR

Manufacturer's Classification

Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)