Datasheet Texas Instruments 5962-9466902QXC
| Manufacturer | Texas Instruments |
| Series | SMJ320C40 |
| Part Number | 5962-9466902QXC |
Floating-Point Digital Signal Processors, Military 325-CPGA -55 to 125
Datasheets
SMJ320C40, TMP320C40 Digital Signal Processors datasheet
PDF, 1.3 Mb, Revision: H, File published: Oct 12, 2001
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 325 | 325 | 325 |
| Package Type | GF | GF | GF |
| Industry STD Term | CPGA | CPGA | CPGA |
| JEDEC Code | S-CPGA-P | S-CPGA-P | S-CPGA-P |
| Package QTY | 1 | 1 | 1 |
| Carrier | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) | JEDEC TRAY (5+1) |
| Device Marking | C | SMJ320C40GFM40 | 5962-9466902QX |
| Width (mm) | 47.25 | 47.25 | 47.25 |
| Length (mm) | 47.25 | 47.25 | 47.25 |
| Thickness (mm) | 3.62 | 3.62 | 3.62 |
| Pitch (mm) | 1.27 | 1.27 | 1.27 |
| Max Height (mm) | 5.59 | 5.59 | 5.59 |
| Mechanical Data | Download | Download | Download |
Parametrics
| Cycle Time | 33 ns |
| DMA | 6 Ch |
| Data / Program Memory Space | 4G Words |
| Frequency | 60 MHz |
| MIPS | 30 |
| MOPS | 60 |
| Operating Temperature Range | -55 to 100,-55 to 125 C |
| Package Group | CPGA |
| Pin/Package | 325CPGA, 352CFP |
| Rating | Military |
Eco Plan
| RoHS | See ti.com |
Application Notes
- 320C3x 320C4x and 320MCM42x Power-Up Sensitivity at Cold Temperatures (Rev. D)PDF, 248 Kb, Revision: D, File published: Aug 6, 2004
System board-level design and end-equipment environments can impact the operation of specific commercial and military 320C3x (320C30 320C31 320LC31 320C32 and 320VC33) 320C4x (320C40 and 320C44) digital signal processors (DSPs) and the military 320MCM42x (320MCM42C and 320MCM42D) multichip modules (MCMs) during power up. The 320MCM42x MCM incorporates two 320C40 DSP die.Specifically the s - Parallel Digital Signal Processing With the TMS320C40PDF, 175 Kb, File published: Feb 1, 1994
This paper examines parallel processing using the Texas Instruments TMS320C40 floating-point processor. It demonstrates popular parallel architecture topologies such as hypercube, mesh, ring, and pyramid with the ?C40 and discusses the tradeoffs and performance of these ?C40-based architectures. Thispaper is divided into the following sections: OverviewTells why the ?C40 architecture is ide - Parallel Processing With TMS320C4xPDF, 1.3 Mb, File published: Feb 1, 1994
This document presents an in depth discussion of the TMS320C40 ('C40) digital signal processor (DSP), an introduction to parallel processing, hardware applications, software algorithms, and end-applications for the 'C40 32-bit floating-point DSP. The hardware applications prototype the 'C40 to the CYPRESS VICo68/VAC068 Interface and AMELLIA, an A/D or D/A interface to the TMS320C40 global bus. The - Calculation of TMS320C40 Power DissipationPDF, 169 Kb, File published: Nov 1, 1993
The TMS320C40 (?C40) DSP is a high-performance, 32-bit floating-point parallel processor with CMOS technology. The ?C40 power supply currents vary with the specific application and device program activity. This document shows the user how to determine power supply current for the ?C40 under various operating conditions. Once the current is determined, power dissapation can be calculated, followed - Setting Up TMS320 DSP Interrupts in 'C'PDF, 168 Kb, File published: Nov 1, 1994
Four steps are required to set the TMS320 DSP interrupts: create a interrupt service routine initialize the vector table and set the memory map enable the interrupts in the CPU and enable the interrupt sources. This document shows how to set the interrupts in C C callable assembly or in-line C. Sample C code segments are provided. The appendix gives complete examples for setting interrupt vec - Parallel 2-D FFT Implementation With TMS320C4x DSPs (Rev. A)PDF, 295 Kb, Revision: A, File published: Feb 1, 1994
This document provides a brief review of the fast Fourier transform (FFT) algorithm and its extension to two dimensions, then focuses on parallel implementations of 2-D FFTs. It presents a TMS320C40 32-bit parallel digital signal processor (DSP) implementation of parallel 2-D FFT using the TMS320C40 development tool (PPDS). The appendices provide the C and TMS320C40 assembler source code for perfo
Model Line
Series: SMJ320C40 (14)
Manufacturer's Classification
- Semiconductors > Processors > Digital Signal Processors > Other High Reliability DSPs
Other Names:
59629466902QXC, 5962 9466902QXC
