Datasheet Texas Instruments CD74AC109EE4
| Manufacturer | Texas Instruments |
| Series | CD74AC109 |
| Part Number | CD74AC109EE4 |
Dual Positive-Edge-Triggered J-K Flip-Flops with Set and Reset 16-PDIP -55 to 125
Datasheets
CD54AC109, CD74AC109 datasheet
PDF, 901 Kb, File published: Jan 24, 2003
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 16 |
| Package Type | N |
| Industry STD Term | PDIP |
| JEDEC Code | R-PDIP-T |
| Package QTY | 25 |
| Carrier | TUBE |
| Device Marking | CD74AC109E |
| Width (mm) | 6.35 |
| Length (mm) | 19.3 |
| Thickness (mm) | 3.9 |
| Pitch (mm) | 2.54 |
| Max Height (mm) | 5.08 |
| Mechanical Data | Download |
Parametrics
| Bits | 2 |
| F @ Nom Voltage(Max) | 100 Mhz |
| ICC @ Nom Voltage(Max) | 0.04 mA |
| Output Drive (IOL/IOH)(Max) | -24/24 mA |
| Package Group | PDIP |
| Package Size: mm2:W x L | See datasheet (PDIP) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | AC |
| VCC(Max) | 5.5 V |
| VCC(Min) | 1.5 V |
| Voltage(Nom) | 3.3,5 V |
| tpd @ Nom Voltage(Max) | 11.1 ns |
Eco Plan
| RoHS | Compliant |
| Pb Free | Yes |
Application Notes
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, File published: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren
Model Line
Series: CD74AC109 (3)
- CD74AC109E CD74AC109EE4 CD74AC109M96
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop
