Datasheet Texas Instruments DAC5675AIPHP

Manufacturer	Texas Instruments
Series	DAC5675A
Part Number	DAC5675AIPHP

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Design Kits & Evaluation Modules

• Evaluation Modules & Boards: DAC5675AEVM
  DAC5675A 14-Bit, 400-MSPS Digital-to-Analog Converter Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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• Evaluation Modules & Boards: TSW2200EVM
  TSW2200 Low-Cost Portable Power Supply Evaluation Module
  Lifecycle Status: Active (Recommended for new designs)
  
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Application Notes

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  Interfacing op amps to high-speed DACs, Part 1: Current-sinking DACs
  PDF, 319 Kb, File published: Jul 14, 2009
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  Passive Terminations for Current Output DACs
  PDF, 244 Kb, File published: Nov 10, 2008
  The correct implementation of the high-speed DAC output termination is critical to achieving the best possible performance. The typical application involves choosing the correct network to create the necessary dc bias levels and correct effective impedance load to keep the output voltage within the compliance levels. This ensures that the maximum output signal amplitude and optimum ac performance
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  Design for a Wideband Differential Transimpedance DAC Output (Rev. A)
  PDF, 438 Kb, Revision: A, File published: Oct 17, 2016
  High-speed digital-to-analog converters commonly offer a complementary current output signal. Most output interface implementations use either a resistive load and/or a transformer to convert this current source signal to a voltage. Where a dc-coupled interface is required, a carefully designed differential transimpedance stage can offer an attractive alternative. Design considerations and options
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  Q3 2009 Issue Analog Applications Journal
  PDF, 2.1 Mb, File published: Jul 14, 2009
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  High Speed Digital-to-Analog Converters Basics (Rev. A)
  PDF, 829 Kb, Revision: A, File published: Oct 23, 2012
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  Wideband Complementary Current Output DAC Single-Ended Interface
  PDF, 597 Kb, File published: Jun 21, 2005
  High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
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  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, File published: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
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  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, File published: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers

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Manufacturer's Classification

• Semiconductors > Data Converters > Digital-to-Analog Converters (DACs) > High Speed DACs (>10MSPS)