Datasheet Texas Instruments TLV1578CDARG4
| Manufacturer | Texas Instruments |
| Series | TLV1578 |
| Part Number | TLV1578CDARG4 |
8-Ch. 10-Bit 1.25 MSPS ADC 8-Ch., DSP/SPI, Hardware Configurable, Low Power 32-TSSOP 0 to 70
Datasheets
2.7 V to 5.5 V, 1-/-8 Channel 10-Bit Parallel Analog-to-Digital Converters datasheet
PDF, 627 Kb, Revision: D, File published: Jul 11, 2000
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Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 32 |
| Package Type | DA |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | TLV1578 |
| Width (mm) | 6.2 |
| Length (mm) | 11 |
| Thickness (mm) | 1.15 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| # Input Channels | 8 |
| Analog Voltage AVDD(Max) | 5.5 V |
| Analog Voltage AVDD(Min) | 2.7 V |
| Architecture | SAR |
| Digital Supply(Max) | 5.5 V |
| Digital Supply(Min) | 2.7 V |
| INL(Max) | 1 +/-LSB |
| Input Range(Max) | 5.5 V |
| Input Type | Single-Ended |
| Integrated Features | Oscillator |
| Interface | Parallel |
| Multi-Channel Configuration | Multiplexed |
| Operating Temperature Range | -40 to 85,0 to 70 C |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 32TSSOP: 89 mm2: 8.1 x 11(TSSOP) PKG |
| Power Consumption(Typ) | 12 mW |
| Rating | Catalog |
| Reference Mode | Ext |
| Resolution | 10 Bits |
| SINAD | 60 dB |
| SNR | 60 dB |
| Sample Rate (max) | 1.25MSPS SPS |
| Sample Rate(Max) | 1.25 MSPS |
| THD(Typ) | -60 dB |
Eco Plan
| RoHS | Compliant |
Application Notes
- Interfacing the TLV1571/78 Analog-to-Digital Converter to the TMS320C542 DSPPDF, 192 Kb, File published: Oct 7, 1999
This application report presents a hardware solution for interfacing the TLV1571/TLV1578 10-bit, 1.25 MSPS low-power analog-to-digital converter (ADC) to the 16-bit fixed-point TMS320C542 digital signal processor (DSP). The report describes the interface hardware and C-callable software routines, which support communication between ADC and DSP. - Determining Minimum Acquisition Times for SAR ADCs, part 1 (Rev. A)PDF, 227 Kb, Revision: A, File published: Nov 10, 2010
This application report analyzes a simple method for calculating minimum acquisition times for successive-approximation register analog-to-digital converters (SAR ADCs). The input structure of the ADC is examined along with the driving circuit. The voltage on the sampling capacitor is then determined for the case when a step function is applied to the input of the driving circuit. Three different - Determining Minimum Acquisition Times for SAR ADCs, part 2PDF, 215 Kb, File published: Mar 17, 2011
The input structure circuit of a successive-approximation register analog-to-digital converter (SAR ADC) incombination with the driving circuit forms a transfer function that can be used to determine minimum acquisition times for different types of applied input signals. This application report, which builds on Determining Minimum Acquisition Times for SAR ADCs When a Step Function is Applied to
Model Line
Series: TLV1578 (6)
- TLV1578CDA TLV1578CDAG4 TLV1578CDAR TLV1578CDARG4 TLV1578IDA TLV1578IDAG4
Manufacturer's Classification
- Semiconductors > Data Converters > Analog-to-Digital Converters (ADCs) > Precision ADCs (<=10MSPS)
