Datasheet Texas Instruments SN74HC112DR
| Manufacturer | Texas Instruments |
| Series | SN74HC112 |
| Part Number | SN74HC112DR |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-SOIC -40 to 85
Datasheets
SN54HC112, SN74HC112 datasheet
PDF, 598 Kb, Revision: F, File published: Sep 26, 2003
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 16 |
| Package Type | D |
| Industry STD Term | SOIC |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2500 |
| Carrier | LARGE T&R |
| Device Marking | HC112 |
| Width (mm) | 3.91 |
| Length (mm) | 9.9 |
| Thickness (mm) | 1.58 |
| Pitch (mm) | 1.27 |
| Max Height (mm) | 1.75 |
| Mechanical Data | Download |
Parametrics
| Bits | 2 |
| F @ Nom Voltage(Max) | 70 Mhz |
| ICC @ Nom Voltage(Max) | 0.04 mA |
| Output Drive (IOL/IOH)(Max) | -4/4 mA |
| Package Group | SOIC |
| Package Size: mm2:W x L | 16SOIC: 59 mm2: 6 x 9.9(SOIC) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | HC |
| VCC(Max) | 6 V |
| VCC(Min) | 2 V |
| Voltage(Nom) | 3.3,5 V |
| tpd @ Nom Voltage(Max) | 41 ns |
Eco Plan
| RoHS | Compliant |
Application Notes
- HCMOS Design Considerations (Rev. A)PDF, 207 Kb, Revision: A, File published: Sep 9, 2002
This document describes a potential problem designers may encounter when using high-speed CMOS (HC) logic devices. There also is a broad range of CMOS-system to non-CMOS-system interfaces that need to be considered. The design engineer inevitably encounters these interfaces. Key considerations for handling these interfaces are also discussed in this book.
Model Line
Series: SN74HC112 (9)
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop
