Datasheet Texas Instruments SN74ALS112AN3
| Manufacturer | Texas Instruments |
| Series | SN74ALS112A |
| Part Number | SN74ALS112AN3 |
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear and Preset 16-PDIP 0 to 70
Datasheets
Dual J-K Negative-Edge-Triggered Flip-Flops With Clear And Preset datasheet
PDF, 988 Kb, Revision: A, File published: Dec 1, 1994
Extract from the document
Prices
Status
| Lifecycle Status | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 16 |
| Package Type | N |
| Industry STD Term | PDIP |
| JEDEC Code | R-PDIP-T |
| Width (mm) | 6.35 |
| Length (mm) | 19.3 |
| Thickness (mm) | 3.9 |
| Pitch (mm) | 2.54 |
| Max Height (mm) | 5.08 |
| Mechanical Data | Download |
Parametrics
| Approx. Price (US$) | 0.44 | 1ku |
| Bits(#) | 2 |
| F @ Nom Voltage(Max)(Mhz) | 75 |
| ICC @ Nom Voltage(Max)(mA) | 4.5 |
| Input Type | TTL |
| Output Drive (IOL/IOH)(Max)(mA) | -0.4/8 |
| Output Type | TTL |
| Package Group | PDIP |
| Package Size: mm2:W x L (PKG) | See datasheet (PDIP) |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | ALS |
| VCC(Max)(V) | 5.5 |
| VCC(Min)(V) | 4.5 |
| Voltage(Nom)(V) | 5 |
| tpd @ Nom Voltage(Max)(ns) | 18 |
Eco Plan
| RoHS | Not Compliant |
| Pb Free | No |
Application Notes
- Advanced Schottky (ALS and AS) Logic FamiliesPDF, 1.9 Mb, File published: Aug 1, 1995
This document introduces the advanced Schottky family of clamped TTL integrated circuits (ICs). Detailed electrical characteristics of the 'AS and 'ALS devices with table formats are provided. Guidelines for designing high-performance digital systems using the Advanced Schottky family are given along with a brief summary of the solutions to most design decisions needed to implement systems using t
Model Line
Series: SN74ALS112A (5)
- SN74ALS112AD SN74ALS112ADR SN74ALS112AN SN74ALS112AN3 SN74ALS112ANSR
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > J-K Flip-Flop
