Datasheet Texas Instruments ADC10D1000QML-SP
| Manufacturer | Texas Instruments |
| Series | ADC10D1000QML-SP |
Low Power, 10-Bit, Dual 1.0 GSPS or Single 2.0 GSPS A/D Converter
Datasheets
ADC10D1000QML Low-Power, 10-Bit, Dual 1-GSPS or Single 2-GSPS Analog-to-Digital Converter datasheet
PDF, 1.3 Mb, Revision: G, File published: Dec 7, 2016
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Prices
Status
| ADC10D1000CCMLS | ADC10D1000CCMPR | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No |
Packaging
| ADC10D1000CCMLS | ADC10D1000CCMPR | |
|---|---|---|
| N | 1 | 2 |
| Pin | 376 | 376 |
| Package Type | NAA | NAA |
| Industry STD Term | CCGA | CCGA |
| JEDEC Code | S-CBGA-N | S-CBGA-N |
| Package QTY | 1 | 1 |
| Device Marking | ADC10D1000CCMLS | ES |
| Width (mm) | 27.94 | 27.94 |
| Length (mm) | 27.94 | 27.94 |
| Thickness (mm) | 2.79 | 2.79 |
| Pitch (mm) | 1.27 | 1.27 |
| Max Height (mm) | 3.5 | 3.5 |
| Mechanical Data | Download | Download |
Parametrics
| Parameters / Models | ADC10D1000CCMLS | ADC10D1000CCMPR |
|---|---|---|
| # Input Channels | 2,1 | 2,1 |
| Analog Voltage AVDD(Max), V | 2.2 | 2.2 |
| Analog Voltage AVDD(Min), V | 1.8 | 1.8 |
| Architecture | Folding Interpolating | Folding Interpolating |
| ENOB, Bits | 9 | 9 |
| INL(Max), +/-LSB | 0.7 | 0.7 |
| INL(Typ), +/-LSB | 0.7 | 0.7 |
| Interface | Parallel LVDS | Parallel LVDS |
| Operating Temperature Range, C | -55 to 125,25 | -55 to 125,25 |
| Package Group | CCGA | CCGA |
| Package Size: mm2:W x L, PKG | 376CCGA: 781 mm2: 27.94 x 27.94(CCGA) | 376CCGA: 781 mm2: 27.94 x 27.94(CCGA) |
| Power Consumption(Typ), mW | 2900 | 2900 |
| Rating | Space | Space |
| Reference Mode | Int | Int |
| Resolution, Bits | 10 | 10 |
| SFDR, dB | 63 | 63 |
| SNR, dB | 56.8 | 56.8 |
| Sample Rate (max), SPS | 2GSPS | 2GSPS |
Eco Plan
| ADC10D1000CCMLS | ADC10D1000CCMPR | |
|---|---|---|
| RoHS | See ti.com | See ti.com |
Application Notes
- Signal Chain Noise Figure AnalysisPDF, 615 Kb, File published: Oct 29, 2014
- Synchronizing the Giga-Sample ADCs Interfaced with Multiple FPGAsPDF, 943 Kb, File published: Aug 6, 2014
- AN-2128 ADC1xD1x00 Pin Compatibility (Rev. C)PDF, 60 Kb, Revision: C, File published: May 1, 2013
In order to facilitate upgrading applications from a 10-bit Gig ADC to a 12-bit Gig ADC, the ADC10D1x00(ADC10D1500/ADC10D1000) is designed to be pin-compatible with the ADC12D1x00(ADC12D1800/1600/1000). This means that a single board layout may be designed with both resolutionADCs in mind for more cost efficient and time-to-market product development. - From Sample Instant to Data Output: Understanding Latency in the GSPS ADCPDF, 392 Kb, File published: Dec 18, 2012
For many applications which use ultra high-speed ADCs, latency can be a critical performance specification. For example, if the ADC is used in any kind of feedback loop, then the absolute latency is an important factor. For a MIMO system such as a phased array radar, the relative difference and variability in latency becomes important. This application note covers latency in the GSPS ADC products, - AN-2132 Synchronizing Multiple GSPS ADCs in a System: The AutoSync Feature (Rev. G)PDF, 169 Kb, Revision: G, File published: Feb 3, 2017
Model Line
Series: ADC10D1000QML-SP (2)
Manufacturer's Classification
- Semiconductors> Space & High Reliability> Data Converter> Analog to Digital Converters
