Datasheet Texas Instruments ADS4249
| Manufacturer | Texas Instruments |
| Series | ADS4249 |
Dual-Channel, 14-Bit, 250-MSPS Analog-to-Digital Converter (ADC)
Datasheets
ADS4249 Dual-Channel, 14-Bit, 250-MSPS Ultralow-Power ADC datasheet
PDF, 2.0 Mb, Revision: E, File published: Jan 7, 2016
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Prices
Status
| ADS4249IRGCR | ADS4249IRGCT | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | No | No |
Packaging
| ADS4249IRGCR | ADS4249IRGCT | |
|---|---|---|
| N | 1 | 2 |
| Pin | 64 | 64 |
| Package Type | RGC | RGC |
| Industry STD Term | VQFN | VQFN |
| JEDEC Code | S-PQFP-N | S-PQFP-N |
| Package QTY | 2000 | 250 |
| Carrier | LARGE T&R | SMALL T&R |
| Device Marking | AZ4249 | AZ4249 |
| Width (mm) | 9 | 9 |
| Length (mm) | 9 | 9 |
| Thickness (mm) | .88 | .88 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1 | 1 |
| Mechanical Data | Download | Download |
Parametrics
| Parameters / Models | ADS4249IRGCR | ADS4249IRGCT |
|---|---|---|
| # Input Channels | 2 | 2 |
| Analog Input BW, MHz | 600 | 600 |
| Architecture | Pipeline | Pipeline |
| DNL(Max), +/-LSB | 1.7 | 1.7 |
| DNL(Typ), +/-LSB | 0.5 | 0.5 |
| ENOB, Bits | 11.7 | 11.7 |
| INL(Max), +/-LSB | 5 | 5 |
| INL(Typ), +/-LSB | 2 | 2 |
| Input Buffer | No | No |
| Input Range, Vp-p | 2 | 2 |
| Interface | DDR LVDS,Parallel CMOS | DDR LVDS,Parallel CMOS |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Package Group | VQFN | VQFN |
| Package Size: mm2:W x L, PKG | 64VQFN: 81 mm2: 9 x 9(VQFN) | 64VQFN: 81 mm2: 9 x 9(VQFN) |
| Power Consumption(Typ), mW | 470 | 470 |
| Rating | Catalog | Catalog |
| Reference Mode | Int | Int |
| Resolution, Bits | 14 | 14 |
| SFDR, dB | 80 | 80 |
| SINAD, dB | 72 | 72 |
| SNR, dB | 72.8 | 72.8 |
| Sample Rate(Max), MSPS | 250 | 250 |
Eco Plan
| ADS4249IRGCR | ADS4249IRGCT | |
|---|---|---|
| RoHS | Compliant | Compliant |
Application Notes
- Signal Chain Noise Figure AnalysisPDF, 615 Kb, File published: Oct 29, 2014
- High-Speed Analog-to-Digital Converter BasicsPDF, 1.1 Mb, File published: Jan 11, 2012
The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil - QFN Layout GuidelinesPDF, 1.3 Mb, File published: Jul 28, 2006
Board layout and stencil information for most Texas Instruments Quad Flat No-Lead (QFN) devices is provided in their data sheets. This document helps printed-circuit board designers understand and better use this information for optimal designs. - Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
- Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
- Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, File published: May 18, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
Model Line
Series: ADS4249 (2)
Manufacturer's Classification
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
