Datasheet Texas Instruments ADS5413

Manufacturer	Texas Instruments
Series	ADS5413

Datasheets

Prices

Status

Packaging

Parametrics

Parameters / Models	ADS5413IPHP
# Input Channels	1
Analog Input BW, MHz	1000
Architecture	Pipeline
DNL(Max), +/-LSB	0.5
DNL(Typ), +/-LSB	0.5
ENOB, Bits	11.3
INL(Max), +/-LSB	1
INL(Typ), +/-LSB	1
Input Buffer	No
Input Range, Vp-p	2.25
Interface	Parallel LVDS
Operating Temperature Range, C	-40 to 85
Package Group	HTQFP
Package Size: mm2:W x L, PKG	48HTQFP: 81 mm2: 9 x 9(HTQFP)
Power Consumption(Typ), mW	400
Rating	Catalog
Reference Mode	Ext,Int
Resolution, Bits	12
SFDR, dB	79
SINAD, dB	67.8
SNR, dB	68.5
Sample Rate(Max), MSPS	65

Eco Plan

Application Notes

• Download
  Standard Procedure Direct Measurement Sub-picosecond RMS Jitter High-Speed ADC
  PDF, 1.0 Mb, File published: Jun 30, 2004
• Download
  How to Calculate the Period Jitter from the SSCR for High-Speed ADCs
  PDF, 218 Kb, File published: Dec 17, 2003
  This document introduces a general formula to translate the phase noise of a clock source, rated via the Single Sideband to Carrier Ratio, to the cycle-to-cycle jitter of the oscillation period. The link allows to seamlessly aggregate the external clock source phase noise, usually given in dBc/Hz, to the phase stability figure of the on-chip clock synchronization circuitry, usually rated in ps-RMS
• Download
  High-Speed Analog-to-Digital Converter Basics
  PDF, 1.1 Mb, File published: Jan 11, 2012
  The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil
• Download
  Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
  PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
• Download
  Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
  PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
• Download
  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, File published: Apr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
• Download
  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
• Download
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, File published: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• Download
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, File published: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
• Download
  Principles of Data Acquisition and Conversion (Rev. A)
  PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
• Download
  A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
  PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
  This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
• Download
  Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
  PDF, 69 Kb, Revision: A, File published: May 18, 2015

Model Line

Manufacturer's Classification

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)