Datasheet Texas Instruments ADS5423
| Manufacturer | Texas Instruments |
| Series | ADS5423 |
14-Bit, 80-MSPS Analog-to-Digital Converter (ADC)
Datasheets
ADS5423: 14-Bit 80 MSPS ADC datasheet
PDF, 1.8 Mb, Revision: A, File published: Jan 14, 2010
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Prices
Status
| ADS5423IPGP | ADS5423IPGPR | ADS5423IPJY | ADS5423IPJYG4 | ADS5423IPJYRG4 | |
|---|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Obsolete (Manufacturer has discontinued the production of the device) | Obsolete (Manufacturer has discontinued the production of the device) | Obsolete (Manufacturer has discontinued the production of the device) |
| Manufacture's Sample Availability | No | No | Yes | No | No |
Packaging
| ADS5423IPGP | ADS5423IPGPR | ADS5423IPJY | ADS5423IPJYG4 | ADS5423IPJYRG4 | |
|---|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 | 5 |
| Pin | 52 | 52 | 52 | 52 | 52 |
| Package Type | PGP | PGP | PJY | PJY | PJY |
| Industry STD Term | HTQFP | HTQFP | QFP | QFP | QFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G | S-PQFP-G | S-PQFP-G | S-PQFP-G |
| Package QTY | 160 | 1000 | |||
| Carrier | JEDEC TRAY (10+1) | LARGE T&R | |||
| Device Marking | ADS5423IPGP | ADS5423IPGP | ADS5423I | ||
| Width (mm) | 10 | 10 | 10 | 10 | 10 |
| Length (mm) | 10 | 10 | 10 | 10 | 10 |
| Thickness (mm) | 1 | 1 | 1.4 | 1.4 | 1.4 |
| Pitch (mm) | .65 | .65 | .65 | .65 | .65 |
| Max Height (mm) | 1.2 | 1.2 | 1.6 | 1.6 | 1.6 |
| Mechanical Data | Download | Download | Download | Download | Download |
Parametrics
| Parameters / Models | ADS5423IPGP | ADS5423IPGPR | ADS5423IPJY | ADS5423IPJYG4 | ADS5423IPJYRG4 |
|---|---|---|---|---|---|
| # Input Channels | 1 | 1 | 1 | 1 | 1 |
| Analog Input BW, MHz | 570 | 570 | |||
| Analog Input BW(MHz) | 570 | 570 | 570 | ||
| Approx. Price (US$) | 44.00 | 1ku | 44.00 | 1ku | 44.00 | 1ku | ||
| Architecture | Pipeline | Pipeline | Pipeline | Pipeline | Pipeline |
| DNL(Max), +/-LSB | 0.5 | 0.5 | |||
| DNL(Max)(+/-LSB) | 0.5 | 0.5 | 0.5 | ||
| DNL(Typ), +/-LSB | 0.5 | 0.5 | |||
| ENOB, Bits | 12.2 | 12.2 | |||
| ENOB(Bits) | 12.2 | 12.2 | 12.2 | ||
| INL(Max), +/-LSB | 1.5 | 1.5 | |||
| INL(Max)(+/-LSB) | 1.5 | 1.5 | 1.5 | ||
| INL(Typ), +/-LSB | 1.5 | 1.5 | |||
| Input Buffer | No | No | |||
| Input Range | 2.2 | 2.2 | 2.2V (p-p) | 2.2V (p-p) | 2.2V (p-p) |
| Interface | Parallel LVDS | Parallel LVDS | Parallel LVDS Serial SPI Interface | Parallel LVDS Serial SPI Interface | Parallel LVDS Serial SPI Interface |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | |||
| Operating Temperature Range(C) | -40 to 85 | -40 to 85 | -40 to 85 | ||
| Package Group | HTQFP | HTQFP | HTQFP | HTQFP | HTQFP |
| Package Size(mm2=WxL) | 52HTQFP: 144 mm2: 12 x 12 | 52HTQFP: 144 mm2: 12 x 12 | 52HTQFP: 144 mm2: 12 x 12 | ||
| Package Size: mm2:W x L, PKG | 52HTQFP: 144 mm2: 12 x 12(HTQFP) | 52HTQFP: 144 mm2: 12 x 12(HTQFP) | |||
| Power Consumption(Typ), mW | 1850 | 1850 | |||
| Power Consumption(Typ)(mW) | 1850 | 1850 | 1850 | ||
| Rating | Catalog | Catalog | Catalog | Catalog | Catalog |
| Reference Mode | Int | Int | Int | Int | Int |
| Resolution, Bits | 14 | 14 | |||
| Resolution(Bits) | 14 | 14 | 14 | ||
| SFDR, dB | 93 | 93 | |||
| SFDR(dB) | 93 | 93 | 93 | ||
| SINAD, dB | 74.2 | 74.2 | |||
| SINAD(dB) | 74.2 | 74.2 | 74.2 | ||
| SNR, dB | 74.3 | 74.3 | |||
| SNR(dB) | 74.3 | 74.3 | 74.3 | ||
| Sample Rate (max)(SPS) | 80MSPS | 80MSPS | 80MSPS | ||
| Sample Rate(Max), MSPS | 80 | 80 |
Eco Plan
| ADS5423IPGP | ADS5423IPGPR | ADS5423IPJY | ADS5423IPJYG4 | ADS5423IPJYRG4 | |
|---|---|---|---|---|---|
| RoHS | Compliant | Compliant | Not Compliant | Not Compliant | Not Compliant |
| Pb Free | No | No | No |
Application Notes
- Clocking High-Speed Data ConvertersPDF, 310 Kb, File published: Jan 18, 2005
- High-Speed Analog-to-Digital Converter BasicsPDF, 1.1 Mb, File published: Jan 11, 2012
The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil - Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
- Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
- Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, File published: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs. - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
- A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference. - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, File published: May 18, 2015
- Clocking High-Speed Data ConvertersPDF, 310 Kb, File published: Jan 18, 2005
- High-Speed, Analog-to-Digital Converter BasicsPDF, 1.1 Mb, File published: Jan 11, 2012
The goal of this document is to introduce a wide range of theories and topics that are relevant to high-speed, analog-to-digital converters (ADC). This document provides details on sampling theory, - Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
ADS6129, ADS6149 Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat - Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
ADS4149 Why Use Oversampling when Undersampling Can Do the Job? - Smart Selection of ADC/DAC Enables Better Design of Software-Defined RadioPDF, 376 Kb, File published: Apr 28, 2009
This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs - Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies - Phase Noise Performance and Jitter Cleaning Ability of CDCE72010PDF, 2.3 Mb, File published: Jun 2, 2008
This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the refe - CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital ConvertersPDF, 424 Kb, File published: Jun 8, 2008
Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed, high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483, which is capable of - Interleaving Analog-to-Digital ConvertersPDF, 64 Kb, File published: Oct 2, 2000
It is tempting when pushing the limits of analog-to-digital conversion to consider interleaving two or more converters to increase the sample rate. However, such designs must take into consideration s - Principles of Data Acquisition and Conversion (Rev. A)PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
AB-082 Principles of Data Acquisition and Conversion - A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (ΔΣ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specificati - Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)PDF, 69 Kb, Revision: A, File published: May 18, 2015
AB-084 Analog-to-Digital Grounding Practices Affect System Performance - What Designers Should Know About Data Converter DriftPDF, 95 Kb, File published: Oct 2, 2000
Exactly how inaccurate will a change in temperature make an analog-to-digital or digital-to-analog converter? As designers are well aware, a 12-bit device may provide a much lower accuracy at its oper
Model Line
Series: ADS5423 (5)
Manufacturer's Classification
- Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)
