Datasheet Texas Instruments ADS5474

ManufacturerTexas Instruments
SeriesADS5474
Datasheet Texas Instruments ADS5474

14-Bit, 400-MSPS Analog-to-Digital Converter (ADC)

Datasheets

ADS5474 14-Bit, 400-MSPS Analog-to-Digital Converter datasheet
PDF, 1.8 Mb, Revision: C, File published: Jan 7, 2016
Extract from the document
ADS5474 14-Bit, 400-MSPS Analog-to-Digital Converter (Rev. C)
PDF, 1.8 Mb, Revision: C, File published: Jan 7, 2016

Prices

Status

ADS5474IPFPADS5474IPFPRADS5474IPFPRG4
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNo

Packaging

ADS5474IPFPADS5474IPFPRADS5474IPFPRG4
N123
Pin808080
Package TypePFPPFPPFP
Industry STD TermHTQFPHTQFPHTQFP
JEDEC CodeS-PQFP-GS-PQFP-GS-PQFP-G
Package QTY9610001000
CarrierJEDEC TRAY (10+1)LARGE T&RLARGE T&R
Device MarkingADS5474IADS5474IADS5474I
Width (mm)121212
Length (mm)121212
Thickness (mm)111
Pitch (mm).5.5.5
Max Height (mm)1.21.21.2
Mechanical DataDownloadDownloadDownload

Parametrics

Parameters / ModelsADS5474IPFP
ADS5474IPFP
ADS5474IPFPR
ADS5474IPFPR
ADS5474IPFPRG4
ADS5474IPFPRG4
# Input Channels111
Analog Input BW, MHz144014401440
ArchitecturePipelinePipelinePipeline
DNL(Max), +/-LSB0.70.70.7
DNL(Typ), +/-LSB0.70.70.7
ENOB, Bits11.211.211.2
INL(Max), +/-LSB111
INL(Typ), +/-LSB111
Input BufferYesYesYes
Input Range, Vp-p2.22.22.2
InterfaceParallel LVDSParallel LVDSParallel LVDS
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85
Package GroupHTQFPHTQFPHTQFP
Package Size: mm2:W x L, PKG80HTQFP: 196 mm2: 14 x 14(HTQFP)80HTQFP: 196 mm2: 14 x 14(HTQFP)80HTQFP: 196 mm2: 14 x 14(HTQFP)
Power Consumption(Typ), mW250025002500
RatingCatalogCatalogCatalog
Reference ModeExt,IntExt,IntExt,Int
Resolution, Bits141414
SFDR, dB868686
SINAD, dB68.968.968.9
SNR, dB70.270.270.2
Sample Rate(Max), MSPS400400400

Eco Plan

ADS5474IPFPADS5474IPFPRADS5474IPFPRG4
RoHSCompliantCompliantCompliant

Application Notes

  • High-Speed Analog-to-Digital Converter Basics
    PDF, 1.1 Mb, File published: Jan 11, 2012
    The goal of this document is to introduce a wide range of theories and topics that are relevant tohigh-speed analog-to-digital converters (ADC). This document provides details on sampling theorydata-sheet specifications ADC selection criteria and evaluation methods clock jitter and other commonsystem-level concerns. In addition some end-users will want to extend the performance capabil
  • Design Considerations for Avoiding Timing Errors during High-Speed ADC, LVDS Dat (Rev. A)
    PDF, 2.0 Mb, Revision: A, File published: May 22, 2015
  • Why Use Oversampling when Undersampling Can Do the Job? (Rev. A)
    PDF, 1.2 Mb, Revision: A, File published: Jul 19, 2013
  • Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
    PDF, 376 Kb, File published: Apr 28, 2009
    This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
  • Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
    PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
    This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
  • Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
    PDF, 2.3 Mb, File published: Jun 2, 2008
    This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
  • CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
    PDF, 424 Kb, File published: Jun 8, 2008
    Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
  • Principles of Data Acquisition and Conversion (Rev. A)
    PDF, 132 Kb, Revision: A, File published: Apr 16, 2015
  • A Glossary of Analog-to-Digital Specifications and Performance Characteristics (Rev. B)
    PDF, 425 Kb, Revision: B, File published: Oct 9, 2011
    This glossary is a collection of the definitions of Texas Instruments' Delta-Sigma (О”ОЈ), successive approximation register (SAR), and pipeline analog-to-digital (A/D) converter specifications and performance characteristics. Although there is a considerable amount of detail in this document, the product data sheet for a particular product specification is the best and final reference.
  • Analog-to-Digital Converter Grounding Practices Affect System Performance (Rev. A)
    PDF, 69 Kb, Revision: A, File published: May 18, 2015

Model Line

Manufacturer's Classification

  • Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)