Datasheet Texas Instruments CD54ACT373F3A

Manufacturer	Texas Instruments
Series	CD54ACT373
Part Number	CD54ACT373F3A

Octal Transparent Latches with 3-State Outputs 20-CDIP -55 to 125

Datasheets

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PDF, 1.3 Mb, File published: Dec 3, 1998

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Data sheet acquired from Harris Semiconductor
SCHS289 This data sheet is applicable to the CD54/74AC373, CD54/74ACT373, and CD54ACT533. The CD74AC533 and CD74ACT533 were not
acquired from Harris Semiconductor. PACKAGE OPTION ADDENDUM www.ti.com 17-Mar-2017 PACKAGING INFORMATION
Orderable Device Status
(1) Package Type Package Pins Package
Drawing
Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (В°C) Device Marking
(4/5) CD54AC373F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 CD54AC373F3A CD54ACT373F3A ACTIVE CDIP J 20 1 TBD A42 N / A for Pkg Type -55 to 125 CD54ACT373F3A CD74AC373E ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74AC373E CD74AC373M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC373M CD74AC373M96 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC373M CD74AC373MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 AC373M CD74ACT373E ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74ACT373E CD74ACT373EE4 ACTIVE PDIP N 20 20 Pb-Free
(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74ACT373E CD74ACT373M ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT373M CD74ACT373M96 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT373M CD74ACT373M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT373M CD74ACT373MG4 ACTIVE SOIC DW 20 25 Green (RoHS
& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 ACT373M (1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device. …

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Status

Lifecycle Status	Active (Recommended for new designs)
Manufacture's Sample Availability	No

Packaging

Pin	20
Package Type	J
Industry STD Term	CDIP
JEDEC Code	R-GDIP-T
Package QTY	1
Carrier	TUBE
Device Marking	CD54ACT373F3A
Width (mm)	6.92
Length (mm)	24.2
Thickness (mm)	4.57
Pitch (mm)	2.54
Max Height (mm)	5.08
Mechanical Data	Download

Parametrics

3-State Output	Yes
Bits	8
F @ Nom Voltage(Max)	90 Mhz
ICC @ Nom Voltage(Max)	0.04 mA
Input Type	TTL
Operating Temperature Range	-55 to 125 C
Output Drive (IOL/IOH)(Max)	24/-24 mA
Output Type	CMOS
Package Group	CDIP
Package Size: mm2:W x L	See datasheet (CDIP) PKG
Rating	Military
Technology Family	ACT
VCC(Max)	5.5 V
VCC(Min)	4.5 V
tpd @ Nom Voltage(Max)	11.5 ns

Eco Plan

RoHS	See ti.com

Application Notes

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Selecting the Right Level Translation Solution (Rev. A)
PDF, 313 Kb, Revision: A, File published: Jun 22, 2004
Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
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CMOS Power Consumption and CPD Calculation (Rev. B)
PDF, 89 Kb, Revision: B, File published: Jun 1, 1997
Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
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Power-Up Behavior of Clocked Devices (Rev. A)
PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
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Designing With Logic (Rev. C)
PDF, 186 Kb, Revision: C, File published: Jun 1, 1997
Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
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Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
PDF, 43 Kb, File published: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Model Line

Series: CD54ACT373 (1)

CD54ACT373F3A

Manufacturer's Classification

Semiconductors > Space & High Reliability > Logic Products > Flip-Flop/Latch/Registers