Datasheet Texas Instruments 5962-8943601MRA
Manufacturer | Texas Instruments |
Series | CD54HCT299 |
Part Number | 5962-8943601MRA |
High Speed CMOS Logic 8-Bit Universal Shift Register with 3-State Outputs 20-CDIP -55 to 125
Datasheets
CD54HC299, CD74HC299, CD54HCT299, CD74HCT299 datasheet
PDF, 865 Kb, Revision: C, File published: Apr 16, 2003
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Status
Lifecycle Status | Active (Recommended for new designs) |
Manufacture's Sample Availability | No |
Packaging
Pin | 20 |
Package Type | J |
Industry STD Term | CDIP |
JEDEC Code | R-GDIP-T |
Package QTY | 1 |
Carrier | TUBE |
Width (mm) | 6.92 |
Length (mm) | 24.2 |
Thickness (mm) | 4.57 |
Pitch (mm) | 2.54 |
Max Height (mm) | 5.08 |
Mechanical Data | Download |
Parametrics
3-State Output | Yes |
Bits | 8 |
F @ Nom Voltage(Max) | 25 Mhz |
ICC @ Nom Voltage(Max) | 0.08 mA |
Input Type | TTL |
Operating Temperature Range | -55 to 125 C |
Output Drive (IOL/IOH)(Max) | 4/-4 mA |
Output Type | CMOS |
Package Group | CDIP |
Package Size: mm2:W x L | See datasheet (CDIP) PKG |
Rating | Military |
Technology Family | HCT |
VCC(Max) | 5.5 V |
VCC(Min) | 4.5 V |
tpd @ Nom Voltage(Max) | 56 ns |
Eco Plan
RoHS | See ti.com |
Application Notes
- Semiconductor Packing Material Electrostatic Discharge (ESD) ProtectionPDF, 337 Kb, File published: Jul 8, 2004
Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge - Introduction to LogicPDF, 93 Kb, File published: Apr 30, 2015
- Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)PDF, 614 Kb, Revision: C, File published: Dec 2, 2015
- Using High Speed CMOS and Advanced CMOS in Systems With Multiple VccPDF, 43 Kb, File published: Apr 1, 1996
Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren - SN54/74HCT CMOS Logic Family Applications and RestrictionsPDF, 102 Kb, File published: May 1, 1996
The TI SN54/74HCT family of CMOS devices is a subgroup of the SN74HC series with the HCT circuitry modified to meet the interfacing requirements of TTL outputs to high-speed CMOS inputs. The HCT devices can be driven by the TTL circuits directly without additional components. This document describes the TTL/HC interface the operating voltages circuit noise and power consumption. A Bergeron anal - Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
- Designing With Logic (Rev. C)PDF, 186 Kb, Revision: C, File published: Jun 1, 1997
Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w - CMOS Power Consumption and CPD Calculation (Rev. B)PDF, 89 Kb, Revision: B, File published: Jun 1, 1997
Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale - Implications of Slow or Floating CMOS Inputs (Rev. D)PDF, 260 Kb, Revision: D, File published: Jun 23, 2016
- TI IBIS File Creation Validation and Distribution ProcessesPDF, 380 Kb, File published: Aug 29, 2002
The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
Model Line
Series: CD54HCT299 (2)
- 5962-8943601MRA CD54HCT299F3A
Manufacturer's Classification
- Semiconductors > Space & High Reliability > Logic Products > Flip-Flop/Latch/Registers
Other Names:
59628943601MRA, 5962 8943601MRA