Datasheet Texas Instruments CD74HCT563
Manufacturer | Texas Instruments |
Series | CD74HCT563 |
High Speed CMOS Logic Octal Transparent Inverting Latches with 3-State Outputs
Datasheets
CD54/74HC533, CD54/74HCT533, CD54/74HC563, CD74HCT563 datasheet
PDF, 533 Kb, Revision: C, File published: Jun 20, 2003
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Prices
Status
CD74HCT563E | CD74HCT563M | CD74HCT563ME4 | CD74HCT563MG4 | |
---|---|---|---|---|
Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
Manufacture's Sample Availability | No | No | No | No |
Packaging
CD74HCT563E | CD74HCT563M | CD74HCT563ME4 | CD74HCT563MG4 | |
---|---|---|---|---|
N | 1 | 2 | 3 | 4 |
Pin | 20 | 20 | 20 | 20 |
Package Type | N | DW | DW | DW |
Industry STD Term | PDIP | SOIC | SOIC | SOIC |
JEDEC Code | R-PDIP-T | R-PDSO-G | R-PDSO-G | R-PDSO-G |
Package QTY | 20 | 25 | 25 | 25 |
Carrier | TUBE | TUBE | TUBE | TUBE |
Device Marking | CD74HCT563E | HCT563M | HCT563M | HCT563M |
Width (mm) | 6.35 | 7.5 | 7.5 | 7.5 |
Length (mm) | 24.33 | 12.8 | 12.8 | 12.8 |
Thickness (mm) | 4.57 | 2.35 | 2.35 | 2.35 |
Pitch (mm) | 2.54 | 1.27 | 1.27 | 1.27 |
Max Height (mm) | 5.08 | 2.65 | 2.65 | 2.65 |
Mechanical Data | Download | Download | Download | Download |
Parametrics
Parameters / Models | CD74HCT563E | CD74HCT563M | CD74HCT563ME4 | CD74HCT563MG4 |
---|---|---|---|---|
3-State Output | Yes | Yes | Yes | Yes |
Bits | 8 | 8 | 8 | 8 |
F @ Nom Voltage(Max), Mhz | 25 | 25 | 25 | 25 |
ICC @ Nom Voltage(Max), mA | 0.08 | 0.08 | 0.08 | 0.08 |
Operating Temperature Range, C | -55 to 125 | -55 to 125 | -55 to 125 | -55 to 125 |
Output Drive (IOL/IOH)(Max), mA | 6/-6 | 6/-6 | 6/-6 | 6/-6 |
Package Group | PDIP | SOIC | SOIC | SOIC |
Package Size: mm2:W x L, PKG | See datasheet (PDIP) | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) | 20SOIC: 132 mm2: 10.3 x 12.8(SOIC) |
Rating | Catalog | Catalog | Catalog | Catalog |
Schmitt Trigger | No | No | No | No |
Technology Family | HCT | HCT | HCT | HCT |
VCC(Max), V | 5.5 | 5.5 | 5.5 | 5.5 |
VCC(Min), V | 4.5 | 4.5 | 4.5 | 4.5 |
Voltage(Nom), V | 5 | 5 | 5 | 5 |
tpd @ Nom Voltage(Max), ns | 40 | 40 | 40 | 40 |
Eco Plan
CD74HCT563E | CD74HCT563M | CD74HCT563ME4 | CD74HCT563MG4 | |
---|---|---|---|---|
RoHS | Compliant | Compliant | Compliant | Compliant |
Pb Free | Yes |
Application Notes
- Power-Up Behavior of Clocked Devices (Rev. A)PDF, 34 Kb, Revision: A, File published: Feb 6, 2015
Model Line
Series: CD74HCT563 (4)
Manufacturer's Classification
- Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Latch