Datasheet Texas Instruments CDC509PWRG4
| Manufacturer | Texas Instruments |
| Series | CDC509 |
| Part Number | CDC509PWRG4 |
3.3V Phase Lock Loop Clock Driver 24-TSSOP 0 to 70
Datasheets
CDC509: 3.3-V Phase-Lock Loop Clock Driver datasheet
PDF, 612 Kb, Revision: C, File published: Dec 2, 2004
Extract from the document
Prices
Status
| Lifecycle Status | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes |
Packaging
| Pin | 24 |
| Package Type | PW |
| Industry STD Term | TSSOP |
| JEDEC Code | R-PDSO-G |
| Package QTY | 2000 |
| Carrier | LARGE T&R |
| Device Marking | CK509 |
| Width (mm) | 4.4 |
| Length (mm) | 7.8 |
| Thickness (mm) | 1 |
| Pitch (mm) | .65 |
| Max Height (mm) | 1.2 |
| Mechanical Data | Download |
Parametrics
| Absolute Jitter (Peak-to-Peak Cycle or Period Jitter) | 200 ps |
| Number of Outputs | 9 |
| Operating Frequency Range(Max) | 125 MHz |
| Operating Frequency Range(Min) | 25 MHz |
| Operating Temperature Range | 0 to 70 C |
| Package Group | TSSOP |
| Package Size: mm2:W x L | 24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP) PKG |
| Rating | Catalog |
| VCC | 3.3 V |
| t(phase error) | 480 ps |
| tsk(o) | 200 ps |
Eco Plan
| RoHS | Compliant |
Application Notes
- High Speed Clock Distribution Design Techniques for CDC 509/516/2509/2510/2516 (Rev. A)PDF, 109 Kb, Revision: A, File published: Sep 23, 1998
The memory bandwidth of high performance microprocessors is increasing at a rapid rate and the future memory bandwidth requirements are expected to keep increasing. The bandwidth requirements of RAM will be satisfied in the near term by using Synchronous DRAM. The need to drive multiple DRAM chips at high speeds with low skew necessitates the use of clock distribution devices with Phase Locked Loo
Model Line
Manufacturer's Classification
- Semiconductors > Clock and Timing > Clock Buffers > Zero Delay Buffers
