Datasheet Texas Instruments CDCE906PWRG4

ManufacturerTexas Instruments
SeriesCDCE906
Part NumberCDCE906PWRG4
Datasheet Texas Instruments CDCE906PWRG4

Programmable 3-PLL Clock Synthesizer / Multiplier / Divider 20-TSSOP 0 to 70

Datasheets

Programmable 3-PLL Clock Synthesizer / Multiplier/Divider datasheet
PDF, 1.7 Mb, Revision: H, File published: Dec 11, 2007
Extract from the document

Prices

Status

Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Packaging

Pin20
Package TypePW
Industry STD TermTSSOP
JEDEC CodeR-PDSO-G
Width (mm)4.4
Length (mm)6.5
Thickness (mm)1
Pitch (mm).65
Max Height (mm)1.2
Mechanical DataDownload

Parametrics

Approx. Price (US$)2.20 | 1ku
Divider RatioUniversal
FunctionClock Synthesizer
Clock Multiplier
Clock Divider
Input LevelCrystal
LVCMOS
Differential
Jitter-Peak to Peak(P-P) or Cycle to Cycle(C-C)60 ps
Operating Temperature Range(C)0 to 70
Output Frequency(Max)(MHz)167
Output LevelLVCMOS
Output Skew(ps)150
Package GroupTSSOP
Package Size: mm2:W x L (PKG)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
RatingCatalog
Special FeaturesIntegrated EEPROM
Multiplier/Divider
Spread Spectrum Clocking (SSC)
VCC(V)3.3

Eco Plan

RoHSNot Compliant
Pb FreeNo

Design Kits & Evaluation Modules

  • Evaluation Modules & Boards: CDCE906-706PROGEVM
    CDCE906 and CDCE706 programmable EVM
    Lifecycle Status: Active (Recommended for new designs)
  • Evaluation Modules & Boards: CDCE906-706PERFEVM
    CDCE906 and CDCE706 EVM
    Lifecycle Status: Active (Recommended for new designs)

Application Notes

  • Recommended Terminations for the Differential Inputs of CDCE906/CDCE706
    PDF, 84 Kb, File published: Aug 10, 2006
    This application report describes how differential signals (LVDS, LVPECL, and HSTL) can be connected to CDCE706/CDCE906 differential inputs directly. The wide common-mode voltage and smaller swing required make the devices so versatile that they can receive any signal without any complicated coupling and biasing circuits.
  • CDCx706/x906 Termination and Signal Integrity Guidelines (Rev. A)
    PDF, 155 Kb, Revision: A, File published: Nov 28, 2007
    This application report shows and evaluates different schemes for the CDCE706, CDCE906, CDC706, and CDC906. Guidelines for optimizing the series termination are discussed. Additionally, this report describes how the CDCx706/x906 family can be used to drive 1.8-V clock inputs.
  • High Speed Layout Guidelines (Rev. A)
    PDF, 762 Kb, Revision: A, File published: Aug 8, 2017
    Thisapplicationreportaddresseshigh-speedsignals,suchas clocksignalsand theirrouting,and givesdesignersa reviewof the importantcoherences.Withsomesimplerules,electromagneticinterferenceproblemscan be minimizedwithoutusingcomplicatedformulasand expensivesimulationtools.Section1givesa shortintroductionto theory,whileSection
  • Clock Recommendations for the DM643x EVM
    PDF, 121 Kb, File published: Nov 29, 2006
    The DM643x evaluation module (EVM) requires several clock frequencies to run the system properly. The current clocking proposal of the low-cost EVM consists of the VCXO chip PI6CX100-27W, the PLL chip PLL1705, several bus drivers, and a few oscillaors and crystals. This application report discusses several optimized clocking proposals with the Texas Instruments new clock drivers and recommends a m
  • Troubleshooting I2C Bus Protocol
    PDF, 184 Kb, File published: Oct 19, 2009
    When using the I2Cв„ў bus protocol, the designer must ensure that the hardware complies with the I2C standard. This application report describes the I2C protocol and provides guidelines on debugging a missing acknowledgment, selecting the pullup resistors, or meeting the maximum capacitance load of an I2C bus. A conflict occurs if devices sharing the I2C bus have the same slave address. This

Model Line

Series: CDCE906 (4)

Manufacturer's Classification

  • Semiconductors > Clock and Timing > Clock Generators > Spread-Spectrum Clocks