Datasheet Texas Instruments CDCLVD1204

ManufacturerTexas Instruments
SeriesCDCLVD1204
Datasheet Texas Instruments CDCLVD1204

Low Jitter, 2-Input Selectable 1:4 Universal-to-LVDS Buffer

Datasheets

CDCLVD1204 2:4 Low Additive Jitter LVDS Buffer datasheet
PDF, 1.3 Mb, Revision: B, File published: Oct 5, 2016
Extract from the document

Prices

Status

CDCLVD1204RGTRCDCLVD1204RGTT
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNo

Packaging

CDCLVD1204RGTRCDCLVD1204RGTT
N12
Pin1616
Package TypeRGTRGT
Industry STD TermVQFNVQFN
JEDEC CodeS-PQFP-NS-PQFP-N
Package QTY3000250
CarrierLARGE T&RSMALL T&R
Device MarkingD1204D1204
Width (mm)33
Length (mm)33
Thickness (mm).9.9
Pitch (mm).5.5
Max Height (mm)11
Mechanical DataDownloadDownload

Parametrics

Parameters / ModelsCDCLVD1204RGTR
CDCLVD1204RGTR
CDCLVD1204RGTT
CDCLVD1204RGTT
Additive RMS Jitter(Typ), fs171171
Input Frequency(Max), MHz800800
Input LevelLVCMOS,LVDS,LVPECLLVCMOS,LVDS,LVPECL
Number of Outputs44
Operating Temperature Range, C-40 to 85-40 to 85
Output Frequency(Max), MHz800800
Output LevelLVDSLVDS
Package GroupVQFNVQFN
Package Size: mm2:W x L, PKG16VQFN: 9 mm2: 3 x 3(VQFN)16VQFN: 9 mm2: 3 x 3(VQFN)
RatingCatalogCatalog
VCC, V2.52.5
VCC Out, V2.52.5

Eco Plan

CDCLVD1204RGTRCDCLVD1204RGTT
RoHSCompliantCompliant

Application Notes

  • Clocking Design Guidelines: Unused Pins
    PDF, 158 Kb, File published: Nov 19, 2015

Model Line

Series: CDCLVD1204 (2)

Manufacturer's Classification

  • Semiconductors> Clock and Timing> Clock Buffers> Differential