Datasheet Texas Instruments CDCM7005

ManufacturerTexas Instruments
SeriesCDCM7005
Datasheet Texas Instruments CDCM7005

High Performance, Low Phase Noise, Low Skew Clock Synchronizer that Synchronizes Ref Clock to VCXO

Datasheets

CDCM7005 3.3-V High Performance Clock Synchronizer and Jitter Cleaner datasheet
PDF, 4.0 Mb, Revision: G, File published: Aug 16, 2017
Extract from the document

Prices

Status

CDCM7005RGZRCDCM7005RGZRG4CDCM7005RGZTCDCM7005RGZTG4CDCM7005ZVACDCM7005ZVARCDCM7005ZVAT
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNoYesYesYesNoNo

Packaging

CDCM7005RGZRCDCM7005RGZRG4CDCM7005RGZTCDCM7005RGZTG4CDCM7005ZVACDCM7005ZVARCDCM7005ZVAT
N1234567
Pin48484848646464
Package TypeRGZRGZRGZRGZZVAZVAZVA
Industry STD TermVQFNVQFNVQFNVQFNBGABGABGA
JEDEC CodeS-PQFP-NS-PQFP-NS-PQFP-NS-PQFP-NS-PBGA-NS-PBGA-NS-PBGA-N
Package QTY250025002502503481000250
CarrierLARGE T&RLARGE T&RSMALL T&RSMALL T&RJEDEC TRAY (10+1)LARGE T&RSMALL T&R
Device MarkingCDCM7005CDCM7005CDCM7005CDCM7005CDCM7005CDCM7005CDCM7005
Width (mm)7777888
Length (mm)7777888
Thickness (mm).9.9.9.9.96.96.96
Pitch (mm).5.5.5.5.8.8.8
Max Height (mm)11111.41.41.4
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownloadDownload

Parametrics

Parameters / ModelsCDCM7005RGZR
CDCM7005RGZR
CDCM7005RGZRG4
CDCM7005RGZRG4
CDCM7005RGZT
CDCM7005RGZT
CDCM7005RGZTG4
CDCM7005RGZTG4
CDCM7005ZVA
CDCM7005ZVA
CDCM7005ZVAR
CDCM7005ZVAR
CDCM7005ZVAT
CDCM7005ZVAT
Divider Ratio1 to 161 to 161 to 161 to 161 to 161 to 161 to 16
Input LevelLVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)LVCMOS (REF_CLK),LVPECL (VCXO_CLK)
Number of Inputs2222222
Number of Outputs5555555
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Output Frequency(Max), MHz1500150015001500150015001500
Output LevelLVCMOS,LVPECLLVCMOS,LVPECLLVCMOS,LVPECLLVCMOS,LVPECLLVCMOS,LVPECLLVCMOS,LVPECLLVCMOS,LVPECL
Package GroupVQFNVQFNVQFNVQFNBGABGABGA
Package Size: mm2:W x L, PKG48VQFN: 49 mm2: 7 x 7(VQFN)48VQFN: 49 mm2: 7 x 7(VQFN)48VQFN: 49 mm2: 7 x 7(VQFN)48VQFN: 49 mm2: 7 x 7(VQFN)64BGA: 64 mm2: 8 x 8(BGA)64BGA: 64 mm2: 8 x 8(BGA)64BGA: 64 mm2: 8 x 8(BGA)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Special FeaturesProgrammable DelayProgrammable DelayProgrammable DelayProgrammable DelayProgrammable DelayProgrammable DelayProgrammable Delay
Supply Voltage(Max), V3.63.63.63.63.63.63.6
Supply Voltage(Min), V3333333

Eco Plan

CDCM7005RGZRCDCM7005RGZRG4CDCM7005RGZTCDCM7005RGZTG4CDCM7005ZVACDCM7005ZVARCDCM7005ZVAT
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliant
Pb FreeYesYesYes

Application Notes

  • TLK313x/CDCM7005 Multi-hop Performance
    PDF, 2.4 Mb, File published: Nov 1, 2009
  • Phase Noise/Phase Jitter Performance of CDCM7005
    PDF, 1.1 Mb, File published: Jul 26, 2005

Model Line

Manufacturer's Classification

  • Semiconductors> Clock and Timing> Clock Jitter Cleaners> Single-Loop PLL