Datasheet Texas Instruments DS92LV18
| Manufacturer | Texas Instruments |
| Series | DS92LV18 |
18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz
Datasheets
DS92LV18 18-Bit Bus LVDS Serializer/Deserializer - 15-66 MHz datasheet
PDF, 1.3 Mb, Revision: E, File published: Apr 18, 2013
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Prices
Status
| DS92LV18TVV/NOPB | DS92LV18TVVX/NOPB | |
|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No |
Packaging
| DS92LV18TVV/NOPB | DS92LV18TVVX/NOPB | |
|---|---|---|
| N | 1 | 2 |
| Pin | 80 | 80 |
| Package Type | PN | PN |
| Industry STD Term | LQFP | LQFP |
| JEDEC Code | S-PQFP-G | S-PQFP-G |
| Package QTY | 119 | 1000 |
| Carrier | TUBE | LARGE T&R |
| Device Marking | DS92LV18TVV | >B |
| Width (mm) | 12 | 12 |
| Length (mm) | 12 | 12 |
| Thickness (mm) | 1.4 | 1.4 |
| Pitch (mm) | .5 | .5 |
| Max Height (mm) | 1.6 | 1.6 |
| Mechanical Data | Download | Download |
Parametrics
| Parameters / Models | DS92LV18TVV/NOPB | DS92LV18TVVX/NOPB |
|---|---|---|
| ESD, kV | 2 | 2 |
| Function | SerDes | SerDes |
| Input Compatibility | LVTTL,BLVDS | LVTTL,BLVDS |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 |
| Output Compatibility | LVDS,BLVDS,LVTTL | LVDS,BLVDS,LVTTL |
| Package Group | LQFP | LQFP |
| Package Size: mm2:W x L, PKG | 80LQFP: 196 mm2: 14 x 14(LQFP) | 80LQFP: 196 mm2: 14 x 14(LQFP) |
| Protocols | Channel-Link I | Channel-Link I |
| Rating | Catalog | Catalog |
| Supply Voltage(s), V | 3.3 | 3.3 |
Eco Plan
| DS92LV18TVV/NOPB | DS92LV18TVVX/NOPB | |
|---|---|---|
| RoHS | Compliant | Compliant |
Application Notes
- External Serial Interface Reduces Simultaneous Switching Output Noise in FPGAs (Rev. A)PDF, 8.3 Mb, Revision: A, File published: Apr 26, 2013
This application report highlights how using external SerDes in conjunction with minimum current driveFPGA I/O can reduce FPGA’s internal noise and reap the benefits of a serial interface across the system.This may allow designers to use low end FPGAs with external SerDes to reduce cost and still have highanalog performance. - DS15BA101 & DS15EA101 Enable Long Reach Applications for Embedded Clock SER/DES (Rev. E)PDF, 170 Kb, Revision: E, File published: Apr 29, 2013
Reduction in system size, increase in system performance and savings in system cost are valuablebenefits that SER/DES devices (Serializers and Deserializers) bring to many system designers. Thesebenefits are the reason why SER/DES are integral pieces of many of today’s high-speed systems.One of the design constraints for these systems is the maximum transmission distance between a serializer
Model Line
Series: DS92LV18 (2)
Manufacturer's Classification
- Semiconductors> Interface> Serializer, Deserializer> BLVDS/LVDS SerDes (<100 MHz)
