Datasheet Texas Instruments OPA4820
| Manufacturer | Texas Instruments |
| Series | OPA4820 |
Quad, Unity-Gain, Low-Noise, Voltage-Feedback Operational Amplifier
Datasheets
Quad, Unity-Gain, Low-Noise, Voltage-Feedback Operational Amplifier datasheet
PDF, 840 Kb, Revision: D, File published: Aug 28, 2008
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Prices
Status
| OPA4820ID | OPA4820IDG4 | OPA4820IDR | OPA4820IPWR | OPA4820IPWT | OPA4820IPWTG4 | |
|---|---|---|---|---|---|---|
| Lifecycle Status | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) | Active (Recommended for new designs) |
| Manufacture's Sample Availability | Yes | No | Yes | No | Yes | Yes |
Packaging
| OPA4820ID | OPA4820IDG4 | OPA4820IDR | OPA4820IPWR | OPA4820IPWT | OPA4820IPWTG4 | |
|---|---|---|---|---|---|---|
| N | 1 | 2 | 3 | 4 | 5 | 6 |
| Pin | 14 | 14 | 14 | 14 | 14 | 14 |
| Package Type | D | D | D | PW | PW | PW |
| Industry STD Term | SOIC | SOIC | SOIC | TSSOP | TSSOP | TSSOP |
| JEDEC Code | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G | R-PDSO-G |
| Package QTY | 50 | 50 | 2500 | 2500 | 250 | 250 |
| Carrier | TUBE | TUBE | LARGE T&R | LARGE T&R | SMALL T&R | SMALL T&R |
| Device Marking | OPA4820 | OPA4820 | OPA4820 | 4820 | 4820 | OPA |
| Width (mm) | 3.91 | 3.91 | 3.91 | 4.4 | 4.4 | 4.4 |
| Length (mm) | 8.65 | 8.65 | 8.65 | 5 | 5 | 5 |
| Thickness (mm) | 1.58 | 1.58 | 1.58 | 1 | 1 | 1 |
| Pitch (mm) | 1.27 | 1.27 | 1.27 | .65 | .65 | .65 |
| Max Height (mm) | 1.75 | 1.75 | 1.75 | 1.2 | 1.2 | 1.2 |
| Mechanical Data | Download | Download | Download | Download | Download | Download |
Parametrics
| Parameters / Models | OPA4820ID | OPA4820IDG4 | OPA4820IDR | OPA4820IPWR | OPA4820IPWT | OPA4820IPWTG4 |
|---|---|---|---|---|---|---|
| 2nd Harmonic, dBc | 84 | 84 | 84 | 84 | 84 | 84 |
| 3rd Harmonic, dBc | 92 | 92 | 92 | 92 | 92 | 92 |
| @ MHz | 1 | 1 | 1 | 1 | 1 | 1 |
| Acl, min spec gain, V/V | 1 | 1 | 1 | 1 | 1 | 1 |
| Additional Features | N/A | N/A | N/A | N/A | N/A | N/A |
| Architecture | Bipolar,Voltage FB | Bipolar,Voltage FB | Bipolar,Voltage FB | Bipolar,Voltage FB | Bipolar,Voltage FB | Bipolar,Voltage FB |
| BW @ Acl, MHz | 650 | 650 | 650 | 650 | 650 | 650 |
| CMRR(Min), dB | 76 | 76 | 76 | 76 | 76 | 76 |
| CMRR(Typ), dB | 85 | 85 | 85 | 85 | 85 | 85 |
| GBW(Typ), MHz | 650 | 650 | 650 | 650 | 650 | 650 |
| Input Bias Current(Max), pA | 20000000 | 20000000 | 20000000 | 20000000 | 20000000 | 20000000 |
| Iq per channel(Max), mA | 5.85 | 5.85 | 5.85 | 5.85 | 5.85 | 5.85 |
| Iq per channel(Typ), mA | 5.6 | 5.6 | 5.6 | 5.6 | 5.6 | 5.6 |
| Number of Channels | 4 | 4 | 4 | 4 | 4 | 4 |
| Offset Drift(Typ), uV/C | 4 | 4 | 4 | 4 | 4 | 4 |
| Operating Temperature Range, C | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 | -40 to 85 |
| Output Current(Typ), mA | 85 | 85 | 85 | 85 | 85 | 85 |
| Package Group | SOIC | SOIC | SOIC | TSSOP | TSSOP | TSSOP |
| Package Size: mm2:W x L, PKG | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14SOIC: 52 mm2: 6 x 8.65(SOIC) | 14TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 14TSSOP: 32 mm2: 6.4 x 5(TSSOP) | 14TSSOP: 32 mm2: 6.4 x 5(TSSOP) |
| Rail-to-Rail | No | No | No | No | No | No |
| Rating | Catalog | Catalog | Catalog | Catalog | Catalog | Catalog |
| Slew Rate(Typ), V/us | 240 | 240 | 240 | 240 | 240 | 240 |
| Total Supply Voltage(Max), +5V=5, +/-5V=10 | 12 | 12 | 12 | 12 | 12 | 12 |
| Total Supply Voltage(Min), +5V=5, +/-5V=10 | 5 | 5 | 5 | 5 | 5 | 5 |
| Vn at 1kHz(Typ), nV/rtHz | 2.5 | 2.5 | 2.5 | 2.5 | 2.5 | 2.5 |
| Vn at Flatband(Typ), nV/rtHz | 2.5 | 2.5 | 2.5 | 2.5 | 2.5 | 2.5 |
| Vos (Offset Voltage @ 25C)(Max), mV | 0.8 | 0.8 | 0.8 | 0.8 | 0.8 | 0.8 |
Eco Plan
| OPA4820ID | OPA4820IDG4 | OPA4820IDR | OPA4820IPWR | OPA4820IPWT | OPA4820IPWTG4 | |
|---|---|---|---|---|---|---|
| RoHS | Compliant | Compliant | Compliant | Compliant | Compliant | Compliant |
Application Notes
- RLC Filter Design for ADC Interface Applications (Rev. A)PDF, 299 Kb, Revision: A, File published: May 13, 2015
As high performance Analog-to-Digital Converters (ADCs) continue to improve in their performance, the last stage interface from the final amplifier into the converter inputs becomes a critical element in the system design if the full converter dynamic range is desired. This application note describes the performance and design equations for a simple passive 2nd-order filter used successfully in AD - ADS5500, OPA695: PC Board Layout for Low Distortion High-Speed ADC DriversPDF, 273 Kb, File published: Apr 22, 2004
Once an analog-to-digital converter (ADC) and a driver/interface have been selected for a given application, the next step to achieving excellent performance is laying out the printed circuit board (PCB) that will support the application. This application report describes several techniques for optimizing a high-speed, 14-bit performance, differential driver PCB layout using a wideband operation - Measuring Board Parasitics in High-Speed Analog DesignPDF, 134 Kb, File published: Jul 7, 2003
Successful circuit designs using high-speed amplifiers can depend upon understanding and identifying parasitic PCB components. Simulating a design while including PCB parasitics can protect against unpleasant production surprises. This application report discusses an easy method for measuring parasitic components in a prototype or final PC board design by using a standard oscilloscope and low freq
Model Line
Series: OPA4820 (6)
Manufacturer's Classification
- Semiconductors> Amplifiers> Operational Amplifiers (Op Amps)> High-Speed Op Amps (>=50MHz)
