Datasheet Texas Instruments SN54ACT374-SP

ManufacturerTexas Instruments
SeriesSN54ACT374-SP
Datasheet Texas Instruments SN54ACT374-SP

Octal D-type Edge-Triggered Flip-Flops With 3-State Outputs

Datasheets

SN54ACT374, SN74ACT374 datasheet
PDF, 1.4 Mb, Revision: F, File published: Nov 1, 2002
Extract from the document

Prices

Status

5962-8763101VSA
Lifecycle StatusActive (Recommended for new designs)
Manufacture's Sample AvailabilityNo

Packaging

5962-8763101VSA
N1
Pin20
Package TypeW
Industry STD TermCFP
JEDEC CodeR-GDFP-F
Package QTY1
CarrierTUBE
Width (mm)6.92
Length (mm)13.09
Thickness (mm)1.84
Pitch (mm)1.27
Max Height (mm)2.45
Mechanical DataDownload

Parametrics

Parameters / Models5962-8763101VSA
5962-8763101VSA
3-State OutputYes
Bits8
F @ Nom Voltage(Max), Mhz90
ICC @ Nom Voltage(Max), mA0.04
Input TypeTTL
Operating Temperature Range, C-55 to 125
Output Drive (IOL/IOH)(Max), mA24/-24
Output TypeCMOS
Package GroupCFP
Package Size: mm2:W x L, PKGSee datasheet (CFP)
RatingSpace
Technology FamilyACT
VCC(Max), V5.5
VCC(Min), V4.5
tpd @ Nom Voltage(Max), ns11.5

Eco Plan

5962-8763101VSA
RoHSSee ti.com

Application Notes

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    PDF, 380 Kb, File published: Aug 29, 2002
    The Input/Output Buffer Information Specification (IBIS) also known as ANSI/EIA-656 has become widely accepted among electronic design automation (EDA) vendors semiconductor vendors and system designers as the format for digital electrical interface data. Because IBIS models do not reveal proprietary internal processes or architectural information semiconductor vendors? support for IBIS con
  • Understanding and Interpreting Standard-Logic Data Sheets (Rev. C)
    PDF, 614 Kb, Revision: C, File published: Dec 2, 2015
  • Semiconductor Packing Material Electrostatic Discharge (ESD) Protection
    PDF, 337 Kb, File published: Jul 8, 2004
    Forty-eight-pin TSSOP components that were packaged using Texas Instruments (TI) standard packing methodology were subjected to electrical discharges between 0.5 and 20 kV as generated by an IEC ESD simulator to determine the level of ISD protection provided by the packing materials. The testing included trays tape and reel and magazines. Additional units were subjected to the same discharge
  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, Revision: A, File published: Jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati
  • Designing With Logic (Rev. C)
    PDF, 186 Kb, Revision: C, File published: Jun 1, 1997
    Data sheets which usually give information on device behavior only under recommended operating conditions may only partially answer engineering questions that arise during the development of systems using logic devices. However information is frequently needed regarding the behavior of the device outside the conditions in the data sheet. Such questions might be:?How does a bus driver behave w
  • Introduction to Logic
    PDF, 93 Kb, File published: Apr 30, 2015
  • Implications of Slow or Floating CMOS Inputs (Rev. D)
    PDF, 260 Kb, Revision: D, File published: Jun 23, 2016
  • CMOS Power Consumption and CPD Calculation (Rev. B)
    PDF, 89 Kb, Revision: B, File published: Jun 1, 1997
    Reduction of power consumption makes a device more reliable. The need for devices that consume a minimum amount of power was a major driving force behind the development of CMOS technologies. As a result CMOS devices are best known for low power consumption. However for minimizing the power requirements of a board or a system simply knowing that CMOS devices may use less power than equivale
  • Using High Speed CMOS and Advanced CMOS in Systems With Multiple Vcc
    PDF, 43 Kb, File published: Apr 1, 1996
    Though low power consumption is a feature of CMOS devices sometimes this feature does not meet a designer?s system power supply constraints. Therefore a partial system power down or multiple Vcc supplies are used to meet the needs of the system. This document shows electrostatic discharge protection circuits. It also provides circuit and bus driver examples of partial system power down and curren

Model Line

Series: SN54ACT374-SP (1)

Manufacturer's Classification

  • Semiconductors> Space & High Reliability> Logic Products> Flip-Flop/Latch/Registers