Datasheet Texas Instruments SN74AVCH8T245

ManufacturerTexas Instruments
SeriesSN74AVCH8T245
Datasheet Texas Instruments SN74AVCH8T245

8-Bit Dual-Supply Bus Transceiver with Configurable Voltage Translation and 3-State Outputs

Datasheets

SN74AVCH8T245 8-Bit Dual-Supply Bus Transceiver With Configurable Level-Shifting, Voltage Translation, and 3-State Outputs datasheet
PDF, 1.1 Mb, Revision: H, File published: Apr 1, 2016
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Prices

Status

74AVCH8T245PWRG474AVCH8T245RHLRG4SN74AVCH8T245DGVRSN74AVCH8T245PWSN74AVCH8T245PWG4SN74AVCH8T245PWRSN74AVCH8T245RHLR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesNoYesNoYesYesYes

Packaging

74AVCH8T245PWRG474AVCH8T245RHLRG4SN74AVCH8T245DGVRSN74AVCH8T245PWSN74AVCH8T245PWG4SN74AVCH8T245PWRSN74AVCH8T245RHLR
N1234567
Pin24242424242424
Package TypePWRHLDGVPWPWPWRHL
Industry STD TermTSSOPVQFNTVSOPTSSOPTSSOPTSSOPVQFN
JEDEC CodeR-PDSO-GR-PQFP-NR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PQFP-N
Package QTY200010002000606020001000
CarrierLARGE T&RLARGE T&RLARGE T&RTUBETUBELARGE T&RLARGE T&R
Device MarkingWP245WP245WP245WP245WP245WP245WP245
Width (mm)4.43.54.44.44.44.43.5
Length (mm)7.85.557.87.87.85.5
Thickness (mm)1.91.05111.9
Pitch (mm).65.5.4.65.65.65.5
Max Height (mm)1.211.21.21.21.21
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownloadDownload

Parametrics

Parameters / Models74AVCH8T245PWRG4
74AVCH8T245PWRG4
74AVCH8T245RHLRG4
74AVCH8T245RHLRG4
SN74AVCH8T245DGVR
SN74AVCH8T245DGVR
SN74AVCH8T245PW
SN74AVCH8T245PW
SN74AVCH8T245PWG4
SN74AVCH8T245PWG4
SN74AVCH8T245PWR
SN74AVCH8T245PWR
SN74AVCH8T245RHLR
SN74AVCH8T245RHLR
Bits8888888
F @ Nom Voltage(Max), Mhz100100100100100100100
ICC @ Nom Voltage(Max), mA0.0160.0160.0160.0160.0160.0160.016
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Package GroupTSSOPVQFNTVSOPTSSOPTSSOPTSSOPVQFN
Package Size: mm2:W x L, PKG24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24VQFN: 19 mm2: 3.5 x 5.5(VQFN)24TVSOP: 32 mm2: 6.4 x 5(TVSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24TSSOP: 50 mm2: 6.4 x 7.8(TSSOP)24VQFN: 19 mm2: 3.5 x 5.5(VQFN)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNo
Technology FamilyAVCAVCAVCAVCAVCAVCAVC
VCC(Max), V3.63.63.63.63.63.63.6
VCC(Min), V1.21.21.21.21.21.21.2
Voltage(Nom), V1.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.31.2,1.5,1.8,2.5,3.3
tpd @ Nom Voltage(Max), ns2.7,2.5,2.4,2.32.7,2.5,2.4,2.32.7,2.5,2.4,2.32.7,2.5,2.4,2.32.7,2.5,2.4,2.32.7,2.5,2.4,2.32.7,2.5,2.4,2.3

Eco Plan

74AVCH8T245PWRG474AVCH8T245RHLRG4SN74AVCH8T245DGVRSN74AVCH8T245PWSN74AVCH8T245PWG4SN74AVCH8T245PWRSN74AVCH8T245RHLR
RoHSCompliantCompliantCompliantCompliantCompliantCompliantCompliant

Application Notes

  • Dynamic Output Control (DOC) Circuitry Technology And Applications (Rev. B)
    PDF, 126 Kb, Revision: B, File published: Jul 7, 1999
    Texas Instruments (TI[TM]) next-generation logic is called the Advanced Very-low-voltage CMOS (AVC) family. The AVCfamily features TI?s Dynamic Output Control (DOC[TM]) circuit (patent pending). DOC circuitry automatically lowers the outputimpedance of the circuit at the beginning of a signal transition, providing enough current to achieve high signaling speeds, thensubsequently raises the i
  • AVC Logic Family Technology and Applications (Rev. A)
    PDF, 148 Kb, Revision: A, File published: Aug 26, 1998
    Texas Instruments (TI?) announces the industry?s first logic family to achieve maximum propagation delays of less than 2 ns at 2.5 V. TI?s next-generation logic is the Advanced Very-low-voltage CMOS (AVC) family. Although optimized for 2.5-V systems, AVC logic supports mixed-voltage systems because it is compatible with 3.3-V and 1.8-V devices. The AVC family features TI?s Dynamic Output Control (
  • Voltage Translation Between 3.3-V, 2.5-V, 1.8-V, and 1.5-V Logic Standards (Rev. B)
    PDF, 390 Kb, Revision: B, File published: Apr 30, 2015
  • 16-Bit Widebus Logic Families in 56-Ball 0.65-mm Pitch Very Thin Fine-Pitch BGA (Rev. B)
    PDF, 895 Kb, Revision: B, File published: May 22, 2002
    TI?s 56-ball MicroStar Jr.E package registered under JEDEC MO-225 has demonstrated through modeling and experimentation that it is an optimal solution for reducing inductance and capacitance improving thermal performance and minimizing board area usage in integrated bus functions. Multiple functions released in the 56-ball MicroStar Jr.E package have superior performance characteristics compa
  • Selecting the Right Level Translation Solution (Rev. A)
    PDF, 313 Kb, Revision: A, File published: Jun 22, 2004
    Supply voltages continue to migrate to lower nodes to support today's low-power high-performance applications. While some devices are capable of running at lower supply nodes others might not have this capability. To haveswitching compatibility between these devices the output of each driver must be compliant with the input of the receiver that it is driving. There are several level-translati

Model Line

Manufacturer's Classification

  • Semiconductors> Logic> Voltage Level Translation> Direction Controlled Voltage Translation