Datasheet Texas Instruments SN74LVT574

ManufacturerTexas Instruments
SeriesSN74LVT574
Datasheet Texas Instruments SN74LVT574

3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs

Datasheets

3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs datasheet
PDF, 837 Kb, Revision: D, File published: Jul 1, 1995
Extract from the document

Prices

Status

SN74LVT574DBLESN74LVT574DBRSN74LVT574DWSN74LVT574DWRSN74LVT574NSRSN74LVT574PWLESN74LVT574PWR
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)Obsolete (Manufacturer has discontinued the production of the device)NRND (Not recommended for new designs)NRND (Not recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Obsolete (Manufacturer has discontinued the production of the device)NRND (Not recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNo

Packaging

SN74LVT574DBLESN74LVT574DBRSN74LVT574DWSN74LVT574DWRSN74LVT574NSRSN74LVT574PWLESN74LVT574PWR
N1234567
Pin20202020202020
Package TypeDBDBDWDWNSPWPW
Industry STD TermSSOPSSOPSOICSOICSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Width (mm)5.35.37.57.55.34.44.4
Length (mm)7.27.212.812.812.66.56.5
Thickness (mm)1.951.952.352.351.9511
Pitch (mm).65.651.271.271.27.65.65
Max Height (mm)222.652.6521.21.2
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownloadDownload
Package QTY2520002000
CarrierTUBELARGE T&RLARGE T&R
Device MarkingLVT574LVT574LX574

Eco Plan

SN74LVT574DBLESN74LVT574DBRSN74LVT574DWSN74LVT574DWRSN74LVT574NSRSN74LVT574PWLESN74LVT574PWR
RoHSNot CompliantNot CompliantCompliantCompliantNot CompliantNot CompliantCompliant
Pb FreeNoNoNoNo

Application Notes

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, File published: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.

Model Line

Manufacturer's Classification

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop