Datasheet Texas Instruments SN74LVTH125

Manufacturer	Texas Instruments
Series	SN74LVTH125

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Parametrics

Parameters / Models	SN74LVTH125D	SN74LVTH125DBR	SN74LVTH125DBRE4	SN74LVTH125DE4	SN74LVTH125DG4	SN74LVTH125DGVR	SN74LVTH125DGVRE4	SN74LVTH125DGVRG4	SN74LVTH125DR	SN74LVTH125DRE4	SN74LVTH125DRG4	SN74LVTH125NSR	SN74LVTH125NSRE4	SN74LVTH125PW	SN74LVTH125PWE4	SN74LVTH125PWG4	SN74LVTH125PWR	SN74LVTH125PWRE4	SN74LVTH125PWRG4	SN74LVTH125RGYR	SN74LVTH125RGYRG4
Bits	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4	4
F @ Nom Voltage(Max), Mhz	160	160	160	160	160	160	160	160	160	160	160	160	160	160	160	160	160	160	160	160	160
ICC @ Nom Voltage(Max), mA	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007	0.007
Operating Temperature Range, C	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85	-40 to 85
Output Drive (IOL/IOH)(Max), mA	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64	-32/64
Package Group	SOIC	SSOP	SSOP	SOIC	SOIC	TVSOP	TVSOP	TVSOP	SOIC	SOIC	SOIC	SO	SO	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	VQFN	VQFN
Package Size: mm2:W x L, PKG	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SSOP: 48 mm2: 7.8 x 6.2(SSOP)	14SSOP: 48 mm2: 7.8 x 6.2(SSOP)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14TVSOP: 23 mm2: 6.4 x 3.6(TVSOP)	14TVSOP: 23 mm2: 6.4 x 3.6(TVSOP)	14TVSOP: 23 mm2: 6.4 x 3.6(TVSOP)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SOIC: 52 mm2: 6 x 8.65(SOIC)	14SO: 80 mm2: 7.8 x 10.2(SO)	14SO: 80 mm2: 7.8 x 10.2(SO)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14TSSOP: 32 mm2: 6.4 x 5(TSSOP)	14VQFN: 12 mm2: 3.5 x 3.5(VQFN)	14VQFN: 12 mm2: 3.5 x 3.5(VQFN)
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Schmitt Trigger	No	No	No	No	No	No	No	No	No	No	No	No	No	No	No	No	No	No	No	No	No
Technology Family	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT	LVT
VCC(Max), V	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6	3.6
VCC(Min), V	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7	2.7
Voltage(Nom), V	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3	3.3
tpd @ Nom Voltage(Max), ns	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5	3.5

Eco Plan

Application Notes

• Download
  Simultaneous-Switching Performance of TI Logic Devices (Rev. B)
  PDF, 378 Kb, Revision: B, File published: Feb 23, 2005
  Simultaneous-switching noise can generate and propagate glitches in electronic systems. Therefore, system designers are faced with challenges to minimize simultaneous-switching noise, while increasing switching speed and improving signal quality. This report presents the performance of different TI logic devices under various simultaneous-switching conditions. Factors such as the number of bits sw
• Download
  LVT Family Characteristics (Rev. A)
  PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
  To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
• Download
  LVT-to-LVTH Conversion
  PDF, 84 Kb, File published: Dec 8, 1998
  Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
• Download
  Bus-Hold Circuit
  PDF, 418 Kb, File published: Feb 5, 2001
  When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Model Line

Manufacturer's Classification

• Semiconductors> Logic> Buffer/Driver/Transceiver> Non-Inverting Buffer/Driver