Datasheet Texas Instruments SN74LVTH240

ManufacturerTexas Instruments
SeriesSN74LVTH240
Datasheet Texas Instruments SN74LVTH240

3.3-V ABT Octal Buffers/Drivers With 3-State Outputs

Datasheets

SN54LVTH240, SN74LVTH240 datasheet
PDF, 1.3 Mb, Revision: K, File published: Sep 11, 2003
Extract from the document

Prices

Status

SN74LVTH240DBLESN74LVTH240DBRSN74LVTH240DWSN74LVTH240DWG4SN74LVTH240DWRSN74LVTH240DWRE4SN74LVTH240GQNRSN74LVTH240NSRSN74LVTH240PWSN74LVTH240PWLESN74LVTH240PWRSN74LVTH240PWRG4
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNoNoNoNoNo

Packaging

SN74LVTH240DBLESN74LVTH240DBRSN74LVTH240DWSN74LVTH240DWG4SN74LVTH240DWRSN74LVTH240DWRE4SN74LVTH240GQNRSN74LVTH240NSRSN74LVTH240PWSN74LVTH240PWLESN74LVTH240PWRSN74LVTH240PWRG4
N123456789101112
Pin202020202020202020202020
Package TypeDBDBDWDWDWDWGQNNSPWPWPWPW
Industry STD TermSSOPSSOPSOICSOICSOICSOICBGA MICROSTAR JUNIORSOPTSSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PBGA-NR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Width (mm)5.35.37.57.57.57.535.34.44.44.44.4
Length (mm)7.27.212.812.812.812.8412.66.56.56.56.5
Thickness (mm)1.951.952.352.352.352.35.751.951111
Pitch (mm).65.651.271.271.271.27.651.27.65.65.65.65
Max Height (mm)222.652.652.652.65121.21.21.21.2
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownload
Package QTY200025252000200020007020002000
CarrierLARGE T&RTUBETUBELARGE T&RLARGE T&RLARGE T&RTUBELARGE T&RLARGE T&R
Device MarkingLXH240LVTH240LVTH240LVTH240LVTH240LXH240LVTH240LXH240LXH240LXH240

Parametrics

Parameters / ModelsSN74LVTH240DBLE
SN74LVTH240DBLE
SN74LVTH240DBR
SN74LVTH240DBR
SN74LVTH240DW
SN74LVTH240DW
SN74LVTH240DWG4
SN74LVTH240DWG4
SN74LVTH240DWR
SN74LVTH240DWR
SN74LVTH240DWRE4
SN74LVTH240DWRE4
SN74LVTH240GQNR
SN74LVTH240GQNR
SN74LVTH240NSR
SN74LVTH240NSR
SN74LVTH240PW
SN74LVTH240PW
SN74LVTH240PWLE
SN74LVTH240PWLE
SN74LVTH240PWR
SN74LVTH240PWR
SN74LVTH240PWRG4
SN74LVTH240PWRG4
Approx. Price (US$)0.31 | 1ku0.31 | 1ku0.31 | 1ku
Bits888888888
Bits(#)888
F @ Nom Voltage(Max), Mhz160160160160160160160160160
F @ Nom Voltage(Max)(Mhz)160160160
ICC @ Nom Voltage(Max), mA0.0050.0050.0050.0050.0050.0050.0050.0050.005
ICC @ Nom Voltage(Max)(mA)0.0050.0050.005
Input TypeCMOS
TTL
CMOS
TTL
CMOS
TTL
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64-32/64
Output Drive (IOL/IOH)(Max)(mA)-32/64-32/64-32/64
Output TypeCMOSCMOSCMOS
Package GroupSSOPSSOPSOICSOICSOICSOICSO
SOIC
SSOP
TSSOP
SOTSSOPTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SO: 98 mm2: 7.8 x 12.6(SO)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
Package Size: mm2:W x L (PKG)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
20SSOP: 56 mm2: 7.8 x 7.2(SSOP)
20SO: 98 mm2: 7.8 x 12.6(SO)
20SOIC: 132 mm2: 10.3 x 12.8(SOIC)
20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.63.63.63.6
VCC(Max)(V)3.63.63.6
VCC(Min), V2.72.72.72.72.72.72.72.72.7
VCC(Min)(V)2.72.72.7
Voltage(Nom), V3.33.33.33.33.33.33.33.33.3
Voltage(Nom)(V)3.33.33.3
tpd @ Nom Voltage(Max), ns4.64.64.64.64.64.64.64.64.6
tpd @ Nom Voltage(Max)(ns)4.64.64.6

Eco Plan

SN74LVTH240DBLESN74LVTH240DBRSN74LVTH240DWSN74LVTH240DWG4SN74LVTH240DWRSN74LVTH240DWRE4SN74LVTH240GQNRSN74LVTH240NSRSN74LVTH240PWSN74LVTH240PWLESN74LVTH240PWRSN74LVTH240PWRG4
RoHSNot CompliantCompliantCompliantCompliantCompliantCompliantNot CompliantCompliantCompliantNot CompliantCompliantCompliant
Pb FreeNoNoNo

Application Notes

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, File published: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, File published: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Model Line

Manufacturer's Classification

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Inverting Buffer/Driver