Datasheet Texas Instruments SN74LVTH32245

ManufacturerTexas Instruments
SeriesSN74LVTH32245
Datasheet Texas Instruments SN74LVTH32245

3.3-V ABT 32-Bit Bus Transceiver With 3-State Outputs

Datasheets

SN74LVTH32245 datasheet
PDF, 779 Kb, Revision: B, File published: Nov 13, 2006
Extract from the document

Prices

Status

SN74LVTH32245GKERSN74LVTH32245ZKER
Lifecycle StatusNRND (Not recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoYes

Packaging

SN74LVTH32245GKERSN74LVTH32245ZKER
N12
Pin9696
Package TypeGKEZKE
Industry STD TermBGA MICROSTARBGA MICROSTAR
JEDEC CodeR-PBGA-NR-PBGA-N
Package QTY10001000
CarrierLARGE T&RLARGE T&R
Device MarkingHV245HV245
Width (mm)5.55.5
Length (mm)13.513.5
Thickness (mm).9.85
Pitch (mm).8.8
Max Height (mm)1.41.4
Mechanical DataDownloadDownload

Parametrics

Parameters / ModelsSN74LVTH32245GKER
SN74LVTH32245GKER
SN74LVTH32245ZKER
SN74LVTH32245ZKER
Bits3232
F @ Nom Voltage(Max), Mhz160160
ICC @ Nom Voltage(Max), mA1010
Operating Temperature Range, C-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA-32/64-32/64
Package GroupLFBGALFBGA
Package Size: mm2:W x L, PKG96LFBGA: 74 mm2: 5.5 x 13.5(LFBGA)96LFBGA: 74 mm2: 5.5 x 13.5(LFBGA)
RatingCatalogCatalog
Schmitt TriggerNoNo
Technology FamilyLVTLVT
VCC(Max), V3.63.6
VCC(Min), V2.72.7
Voltage(Nom), V3.33.3
tpd @ Nom Voltage(Max), ns3.73.7

Eco Plan

SN74LVTH32245GKERSN74LVTH32245ZKER
RoHSSee ti.comCompliant

Application Notes

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, File published: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, File published: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Model Line

Series: SN74LVTH32245 (2)

Manufacturer's Classification

  • Semiconductors> Logic> Buffer/Driver/Transceiver> Standard Transceiver