Datasheet Texas Instruments SN74LVTH32373GKER
| Manufacturer | Texas Instruments |
| Series | SN74LVTH32373 |
| Part Number | SN74LVTH32373GKER |
3.3-V ABT 32-Bit Transparent D-Type Latch With 3-State Outputs 96-LFBGA -40 to 85
Datasheets
SN74LVTH32373 datasheet
PDF, 781 Kb, Revision: B, File published: Dec 1, 2006
Extract from the document
Prices
Status
| Lifecycle Status | NRND (Not recommended for new designs) |
| Manufacture's Sample Availability | No |
Packaging
| Pin | 96 |
| Package Type | GKE |
| Industry STD Term | BGA MICROSTAR |
| JEDEC Code | R-PBGA-N |
| Package QTY | 1000 |
| Carrier | LARGE T&R |
| Device Marking | HV373 |
| Width (mm) | 5.5 |
| Length (mm) | 13.5 |
| Thickness (mm) | .9 |
| Pitch (mm) | .8 |
| Max Height (mm) | 1.4 |
| Mechanical Data | Download |
Parametrics
| 3-State Output | Yes |
| Bits | 32 |
| F @ Nom Voltage(Max) | 160 Mhz |
| ICC @ Nom Voltage(Max) | 10 mA |
| Operating Temperature Range | -40 to 85 C |
| Output Drive (IOL/IOH)(Max) | 64/-32 mA |
| Package Group | LFBGA |
| Package Size: mm2:W x L | 96LFBGA: 74 mm2: 5.5 x 13.5(LFBGA) PKG |
| Rating | Catalog |
| Schmitt Trigger | No |
| Technology Family | LVT |
| VCC(Max) | 3.6 V |
| VCC(Min) | 2.7 V |
| Voltage(Nom) | 3.3 V |
| tpd @ Nom Voltage(Max) | 3.8 ns |
Eco Plan
| RoHS | See ti.com |
Application Notes
- LVT Family Characteristics (Rev. A)PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti - LVT-to-LVTH ConversionPDF, 84 Kb, File published: Dec 8, 1998
Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed. - Bus-Hold CircuitPDF, 418 Kb, File published: Feb 5, 2001
When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of
Model Line
Series: SN74LVTH32373 (2)
- SN74LVTH32373GKER SN74LVTH32373ZKER
Manufacturer's Classification
- Semiconductors > Logic > Flip-Flop/Latch/Register > D-Type Latch
