Datasheet Texas Instruments SN74LVTH374

ManufacturerTexas Instruments
SeriesSN74LVTH374
Datasheet Texas Instruments SN74LVTH374

3.3-V ABT Octal Edge-Triggered D-Type Flip-Flops With 3-State Outputs

Datasheets

SN54LVTH374, SN74LVTH374 datasheet
PDF, 1.2 Mb, Revision: H, File published: Oct 10, 2003
Extract from the document

Prices

Status

SN74LVTH374DBLESN74LVTH374DBRSN74LVTH374DWSN74LVTH374DWE4SN74LVTH374DWG4SN74LVTH374DWRSN74LVTH374NSRSN74LVTH374PWSN74LVTH374PWLESN74LVTH374PWR
Lifecycle StatusObsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Obsolete (Manufacturer has discontinued the production of the device)Active (Recommended for new designs)
Manufacture's Sample AvailabilityNoNoNoNoNoNoNoNoNoNo

Packaging

SN74LVTH374DBLESN74LVTH374DBRSN74LVTH374DWSN74LVTH374DWE4SN74LVTH374DWG4SN74LVTH374DWRSN74LVTH374NSRSN74LVTH374PWSN74LVTH374PWLESN74LVTH374PWR
N12345678910
Pin20202020202020202020
Package TypeDBDBDWDWDWDWNSPWPWPW
Industry STD TermSSOPSSOPSOICSOICSOICSOICSOPTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Width (mm)5.35.37.57.57.57.55.34.44.44.4
Length (mm)7.27.212.812.812.812.812.66.56.56.5
Thickness (mm)1.951.952.352.352.352.351.95111
Pitch (mm).65.651.271.271.271.271.27.65.65.65
Max Height (mm)222.652.652.652.6521.21.21.2
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownloadDownload
Package QTY200025252520002000702000
CarrierLARGE T&RTUBETUBETUBELARGE T&RLARGE T&RTUBELARGE T&R
Device MarkingLXH374LVTH374LVTH374LVTH374LVTH374LVTH374LXH374LXH374

Parametrics

Parameters / ModelsSN74LVTH374DBLE
SN74LVTH374DBLE
SN74LVTH374DBR
SN74LVTH374DBR
SN74LVTH374DW
SN74LVTH374DW
SN74LVTH374DWE4
SN74LVTH374DWE4
SN74LVTH374DWG4
SN74LVTH374DWG4
SN74LVTH374DWR
SN74LVTH374DWR
SN74LVTH374NSR
SN74LVTH374NSR
SN74LVTH374PW
SN74LVTH374PW
SN74LVTH374PWLE
SN74LVTH374PWLE
SN74LVTH374PWR
SN74LVTH374PWR
3-State OutputYesYesYesYesYesYesYesYesYesYes
Approx. Price (US$)0.26 | 1ku0.26 | 1ku
Bits88888888
Bits(#)88
F @ Nom Voltage(Max), Mhz160160160160160160160160
F @ Nom Voltage(Max)(Mhz)160160
ICC @ Nom Voltage(Max), mA55555555
ICC @ Nom Voltage(Max)(mA)55
Input TypeTTLTTL
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85
Output Drive (IOL/IOH)(Max), mA64/-3264/-3264/-3264/-3264/-3264/-3264/-3264/-32
Output Drive (IOL/IOH)(Max)(mA)64/-3264/-32
Output TypeTTLTTL
Package GroupSSOPSSOPSOICSOICSOICSOICSOTSSOPTSSOPTSSOP
Package Size: mm2:W x L, PKG20SSOP: 56 mm2: 7.8 x 7.2(SSOP)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SOIC: 132 mm2: 10.3 x 12.8(SOIC)20SO: 98 mm2: 7.8 x 12.6(SO)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
Package Size: mm2:W x L (PKG)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)20TSSOP: 42 mm2: 6.4 x 6.5(TSSOP)
RatingCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalogCatalog
Schmitt TriggerNoNoNoNoNoNoNoNoNoNo
Technology FamilyLVTLVTLVTLVTLVTLVTLVTLVTLVTLVT
VCC(Max), V3.63.63.63.63.63.63.63.6
VCC(Max)(V)3.63.6
VCC(Min), V2.72.72.72.72.72.72.72.7
VCC(Min)(V)2.72.7
Voltage(Nom), V3.33.33.33.33.33.33.33.3
Voltage(Nom)(V)3.33.3
tpd @ Nom Voltage(Max), ns4.54.54.54.54.54.54.54.5
tpd @ Nom Voltage(Max)(ns)4.54.5

Eco Plan

SN74LVTH374DBLESN74LVTH374DBRSN74LVTH374DWSN74LVTH374DWE4SN74LVTH374DWG4SN74LVTH374DWRSN74LVTH374NSRSN74LVTH374PWSN74LVTH374PWLESN74LVTH374PWR
RoHSNot CompliantCompliantCompliantCompliantCompliantCompliantCompliantCompliantNot CompliantCompliant
Pb FreeNoNo

Application Notes

  • LVT Family Characteristics (Rev. A)
    PDF, 98 Kb, Revision: A, File published: Mar 1, 1998
    To address the need for a complete low-voltage interface solution, Texas Instruments has developed a new generation of logic devices capable of mixed-mode operation. The LVT series relies on a state-of-the-art submicron BiCMOS process to provide up to a 90% reduction in static power dissipation over ABT. LVT devices solve the system need for a transparent seam between the low-voltage and 5-V secti
  • LVT-to-LVTH Conversion
    PDF, 84 Kb, File published: Dec 8, 1998
    Original LVT devices that have bus hold have been redesigned to add the High-Impedance State During Power Up and Power Down feature. Additional devices with and without bus hold have been added to the LVT product line. Design guidelines and issues related to the bus-hold features, switching characteristics, and timing requirements are discussed.
  • Bus-Hold Circuit
    PDF, 418 Kb, File published: Feb 5, 2001
    When designing systems that include CMOS devices, designers must pay special attention to the operating condition in which all of the bus drivers are in an inactive, high-impedance condition (3-state). Unless special measures are taken, this condition can lead to undefined levels and, thus, to a significant increase in the device?s power dissipation. In extreme cases, this leads to oscillation of

Model Line

Manufacturer's Classification

  • Semiconductors> Logic> Flip-Flop/Latch/Register> D-Type Flip-Flop