PDF, 361 Kb, Revision: B, File published: May 5, 2011
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TFP403
TI PanelBusв„ў DIGITAL RECEIVER
SLDS125B -DECEMBER 2000 -REVISED MAY 2011 D Supports Pixel Rates Up to 165MHz
D
D
D
D
D D 4x Over-Sampling for Reduced Bit-Error (Including 1080p and WUXGA at 60 Hz)
Digital Visual Interface (DVI 1.0)
Specification Compliant1
Pin-for-Pin Compatible With TFP501 for
Simple Upgrade Path to HDCP2
True-Color, 24 Bit/Pixel, 16.7M Colors at
1 or 2-Pixels per Clock
Laser Trimmed (50 О©) Input Stage for
Optimum Fixed Impedance Matching
Skew Tolerant up to One Pixel Clock Cycle
(High Clock and Data Jitter Tolerance) D
D
D Rates and Better Performance Over Longer
Cables
Reduced Power Consumption—1.8-V Core
Operation With 3.3 V I/Os and Supplies3 …
