Datasheet Texas Instruments THS1031

Manufacturer	Texas Instruments
Series	THS1031

Datasheets

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Packaging

Parametrics

Parameters / Models	THS1031CDW	THS1031CPW	THS1031CPWR	THS1031CPWRG4	THS1031IDW	THS1031IPW	THS1031IPWG4
# Input Channels	1	1	1	1	1	1	1
Analog Input BW, MHz		150	150
Analog Input BW(MHz)	150			150	150	150	150
Approx. Price (US$)	7.67 | 100u			7.67 | 100u	7.67 | 100u	7.67 | 100u	7.67 | 100u
Architecture	Pipeline	Pipeline	Pipeline	Pipeline	Pipeline	Pipeline	Pipeline
DNL(Max), +/-LSB		1	1
DNL(Max)(+/-LSB)	1			1	1	1	1
DNL(Typ), +/-LSB		0.3	0.3
ENOB, Bits		8.8	8.8
ENOB(Bits)	7.7			7.7	7.7	7.7	7.7
INL(Max), +/-LSB		2	2
INL(Max)(+/-LSB)	2			2	2	2	2
INL(Typ), +/-LSB		1	1
Input Buffer	No	No	No		No	No	No
Input Range	2V (p-p)	2	2	2V (p-p)	2V (p-p)	2V (p-p)	2V (p-p)
Interface	Parallel CMOS	Parallel CMOS	Parallel CMOS	Parallel CMOS	Parallel CMOS	Parallel CMOS	Parallel CMOS
Operating Temperature Range, C		0 to 70	0 to 70
Operating Temperature Range(C)	0 to 70			0 to 70	0 to 70	0 to 70	0 to 70
Package Group	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP	TSSOP
Package Size(mm2=WxL)				28TSSOP: 62 mm2: 6.4 x 9.7
Package Size: mm2:W x L, PKG		28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)	28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Package Size: mm2:W x L (PKG)	28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)				28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)	28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)	28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Power Consumption(Typ), mW		160	160
Power Consumption(Typ)(mW)	160			160	160	160	160
Rating	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog	Catalog
Reference Mode	Ext Int	Ext,Int	Ext,Int	Int Ext	Ext Int	Ext Int	Ext Int
Resolution, Bits		10	10
Resolution(Bits)	10			10	10	10	10
SFDR, dB		52.4	52.4
SFDR(dB)	52.4			52.4	52.4	52.4	52.4
SINAD, dB		56	56
SINAD(dB)	56			56	56	56	56
SNR, dB		49.3	49.3
SNR(dB)	49.3			49.3	49.3	49.3	49.3
Sample Rate (max)(SPS)				30MSPS
Sample Rate(Max), MSPS		30	30
Sample Rate(Max)(MSPS)	30				30	30	30

Eco Plan

Application Notes

• Download
  Using TI FIFOs to Interface High-Speed Data Converters With TI TMS320 DSPs
  PDF, 249 Kb, File published: Jun 8, 2001
  Most high-speed data converters cannot be connected directly to a digital signal processor (DSP). The required transfer rates would tie up most of the DSP's I/O bandwidth. A FIFO is an appropriate solution for this problem because it can buffer a large block of data, and the DSP can read data from the FIFO in a burst mode. This is much more efficient compared to single reads for every sampled valu
• Download
  CDCE62005 as Clock Solution for High-Speed ADCs
  PDF, 805 Kb, File published: Sep 4, 2008
  TI has introduced a family of devices well-suited to meet the demands for high-speed ADC devices such as the ADS5527 which is capable of sampling up to 210 MSPS. To realize the full potential of these high-performance products it is imperative to provide a low phase noise clock source. The CDCE62005 clock synthesizer chip offers a real-world clocking solution to meet these stringent requirements
• Download
  Smart Selection of ADC/DAC Enables Better Design of Software-Defined Radio
  PDF, 376 Kb, File published: Apr 28, 2009
  This application report explains different aspects of selecting analog-to-digital and digital-to-analog data converters for Software-Defined Radio (SDR) applications. It also explains how ADS61xx ADCs and the DAC5688 from Texas Instruments fit properly for SDR designs.
• Download
  Driving High-Speed ADCs: Circuit Topologies and System-Level Parameters (Rev. A)
  PDF, 327 Kb, Revision: A, File published: Sep 10, 2010
  This application report discusses the performance-related aspects of passive and active interfaces at the analog input of high-speed pipeline analog-to-digital converters (ADCs). The report simplifies the many possibilities into two main categories: passive and active interface circuits. The first section of the report gives an overview of equivalent models of buffered and unbuffered ADC input cir
• Download
  Phase Noise Performance and Jitter Cleaning Ability of CDCE72010
  PDF, 2.3 Mb, File published: Jun 2, 2008
  This application report presents phase noise data taken on the CDCE72010 jitter cleaner and synchronizer PLL device. The phase noise performance of the CDCE72010 depends on the phase noise of the reference clock VCXO clock and the CDCE72010 itself. This application report shows the phase noise performance at several of the most popular CDMA frequencies. This data helps the user to choose the rig
• Download
  CDCE72010 as a Clocking Solution for High-Speed Analog-to-Digital Converters
  PDF, 424 Kb, File published: Jun 8, 2008
  Texas Instruments has recently introduced a family of devices suitable to meet the demands of high-speed high-IF sampling analog-to-digital converters (ADCs) such as the ADS5483 which is capable of sampling up to 135 MSPS. To realize the full potential of these high-performance devices the system must provide an extremely low phase noise clock source. The CDCE72010 clock synthesizer chip offers
• Download
  Noise Analysis for High Speed Op Amps (Rev. A)
  PDF, 256 Kb, Revision: A, File published: Jan 17, 2005
  As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

Model Line

Manufacturer's Classification

• Semiconductors> Data Converters> Analog-to-Digital Converters (ADCs)> High Speed ADCs (>10MSPS)