Datasheet Texas Instruments THS5651A

ManufacturerTexas Instruments
SeriesTHS5651A
Datasheet Texas Instruments THS5651A

10-Bit, 125-MSPS Digital-to-Analog Converter (DAC)

Datasheets

10-Bit 125 MSPS CommsDAC <TM> (Rev. A)
PDF, 948 Kb, Revision: A, File published: Sep 25, 2002
10-Bit 125 MSPS CommsDAC datasheet
PDF, 948 Kb, Revision: A, File published: Sep 25, 2002
Extract from the document

Prices

Status

THS5651AIDWTHS5651AIDWG4THS5651AIDWRTHS5651AIPWTHS5651AIPWG4THS5651AIPWR
Lifecycle StatusActive (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)Active (Recommended for new designs)
Manufacture's Sample AvailabilityYesYesYesNoNoNo

Packaging

THS5651AIDWTHS5651AIDWG4THS5651AIDWRTHS5651AIPWTHS5651AIPWG4THS5651AIPWR
N123456
Pin282828282828
Package TypeDWDWDWPWPWPW
Industry STD TermSOICSOICSOICTSSOPTSSOPTSSOP
JEDEC CodeR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-GR-PDSO-G
Package QTY20201000502000
CarrierTUBETUBELARGE T&RTUBELARGE T&R
Device MarkingTHS5651AITHS5651AITHS5651AITJ5651ATJ5651A
Width (mm)7.57.57.54.44.44.4
Length (mm)17.917.917.99.79.79.7
Thickness (mm)2.352.352.35111
Pitch (mm)1.271.271.27.65.65.65
Max Height (mm)2.652.652.651.21.21.2
Mechanical DataDownloadDownloadDownloadDownloadDownloadDownload

Parametrics

Parameters / ModelsTHS5651AIDW
THS5651AIDW
THS5651AIDWG4
THS5651AIDWG4
THS5651AIDWR
THS5651AIDWR
THS5651AIPW
THS5651AIPW
THS5651AIPWG4
THS5651AIPWG4
THS5651AIPWR
THS5651AIPWR
Approx. Price (US$)4.68 | 1ku4.68 | 1ku
ArchitectureCurrent SourceCurrent SourceCurrent SourceCurrent SourceCurrent SourceCurrent Source
DAC Channels11111
DAC: Channels1
InterfaceParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOSParallel CMOS
Interpolation1x1x1x1x1x
Operating Temperature Range, C-40 to 85-40 to 85-40 to 85-40 to 85
Operating Temperature Range(C)-40 to 85-40 to 85
Package GroupSOICSOICSOICTSSOPTSSOPTSSOP
Package Size(mm2=WxL)28SOIC: 184 mm2: 10.3 x 17.9
Package Size: mm2:W x L, PKG28SOIC: 184 mm2: 10.3 x 17.9(SOIC)28SOIC: 184 mm2: 10.3 x 17.9(SOIC)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Package Size: mm2:W x L (PKG)28TSSOP: 62 mm2: 6.4 x 9.7(TSSOP)
Power Consumption(Typ), mW175175175175
Power Consumption(Typ)(mW)175175
RatingCatalogCatalogCatalogCatalogCatalogCatalog
Resolution, Bits10101010
Resolution(Bits)1010
SFDR, dB61616161
SFDR(dB)7777
Sample / Update Rate, MSPS125125125125
Sample / Update Rate(MSPS)125125
Settling Time(?s)0.035

Eco Plan

THS5651AIDWTHS5651AIDWG4THS5651AIDWRTHS5651AIPWTHS5651AIPWG4THS5651AIPWR
RoHSCompliantCompliantCompliantCompliantNot CompliantCompliant
Pb FreeYesNo

Application Notes

  • Wideband Complementary Current Output DAC Single-Ended Interface
    PDF, 597 Kb, File published: Jun 21, 2005
    High-speed digital-to-analog converters (DACs) most often use a transformer-coupled output stage. In applications where this configuration is not practical, a single op ampdifferential to single-ended stage has often been used. This application note steps through the exact design equations required to achieve gain matching from each output as well as a matched input impedance to each of the DA
  • Noise Analysis for High Speed Op Amps (Rev. A)
    PDF, 256 Kb, Revision: A, File published: Jan 17, 2005
    As system bandwidths have increased an accurate estimate of the noise contribution for each element in the signal channel has become increasingly important. Many designers are not however particularly comfortable with the calculations required to predict the total noise for an op amp or in the conversions between the different descriptions of noise. Considerable inconsistency between manufactu

Model Line

Manufacturer's Classification

  • Semiconductors> Data Converters> Digital-to-Analog Converters (DACs)> High Speed DACs (>10MSPS)