This application report describes system design considerations for the TMS320C6472/TMS320TCI6486 (C6472/TCI6486) Digital Signal Processor (DSP). The objective of this document is to simplify the design of the C6472/TCI6486 device into a system/board design. In some cases, there is information overlapping with the TMS320TCI6486 Communications Infrastructure data manual (
PDF, 58 Kb, Revision: A, File published: Sep 17, 2010
This document discusses the power consumption of the Texas Instruments TMS320C6472 digital signal processor (DSP). The power consumption on the TMS320C6472 device is highly application-dependent; therefore, a power spreadsheet that estimates power consumption is provided along with this application report. This spreadsheet can be used to model power consumption for user applications such as pow
PDF, 345 Kb, File published: Dec 23, 2005
The TMS320TCI648x devices introduce a newly designed Enhanced Direct Memory Access (EDMA3). The EDMA3 has many new features that improve system performance and enhance debugging capabilities. This document summarizes the key differences between EDMA3 on the TMS320TCI648x devices and EDMA2 on the TMS320C64x devices. This document also provides guidance for migrating from EDMA2 to EDMA3.
PDF, 452 Kb, File published: Mar 26, 2010
This reference design is intended for designers who wish to design up to eight TMS320C6472 Digital Signal Processors into a system using a nominal input voltage of 5 V, with a flexible design using external FETs, and low-dropout regulators for the low-power rails.
PDF, 251 Kb, File published: Mar 31, 2010
This reference design is intended for designers who wish to design a TMS320C6472 Digital Signal Processor into a system using a nominal input voltage of 5 V, DC/DC converters with integrated FETs, and allowing for ease-of-design and a smaller solution size.
PDF, 441 Kb, File published: Mar 26, 2010
This reference design is intended for designers who wish to design up to eight TMS320C6472 Digital Signal Processors into a system using a nominal input voltage of 12 V, external FETs for design flexibility, and low-dropout regulators for the low-power rails.
PDF, 559 Kb, Revision: A, File published: May 24, 2010
This design was created to help those wanting to design a TMS320C6472 digital signal processor into a system using a nominal input of 12 V, having a highly flexible power design, and the ability to monitor temperature as well as dynamically monitoring and controlling voltage and current.
PDF, 558 Kb, File published: Apr 28, 2010
This design was created to help designers wishing to design up to eight TMS320C6472 Digital Signal Processors into a system using a nominal input voltage of 12 V, having a highly flexible power design, the ability to monitor temperature, and dynamically monitor and control voltage and current.
PDF, 245 Kb, File published: Mar 26, 2010
This reference design is intended for designers who wish to design a TMS320C6472 Digital Signal Processor into a system using a nominal input voltage of 12 V external FETs for design flexibility and low-dropout regulators for the low-power rails.
PDF, 80 Kb, Revision: A, File published: Jul 19, 2013
This application report describes the error detection and correction mechanism of the C64x+/C674x megamodule L1P and L2 memories implemented on some devices. Depending on the type of application, these mechanisms are used to either provide diagnostic measures to detect faults in the memory that could lead to unacceptable risk for the user or to increase the availability of the system.
PDF, 1.8 Mb, Revision: B, File published: Aug 29, 2012
As application complexity continues to grow, we have reached a limit on increasing performance by merely scaling clock speed. To meet the ever-increasing processing demand, modern System-On-Chip solutions contain multiple processing cores. The dilemma is how to map applications to multicore devices. In this paper, we present a programming methodology for converting applications to run on multicore
PDF, 301 Kb, Revision: A, File published: Apr 15, 2003
Today?s high-speed interfaces require strict timings and accurate system design. To achieve the necessary timings for a given system, input/output buffer information specification (IBIS) models must be used. These models accurately represent the device drivers under various process conditions. Board characteristics, such as impedance, loading, length, number of nodes, etc., affect how the device d
PDF, 310 Kb, Revision: A, File published: Oct 20, 2005
This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP
PDF, 535 Kb, File published: Oct 6, 2011
The TMS320C6000™ Digital Signal Processors (DSPs) have many architectural advantages that make them ideal for computation-intensive real-time applications. However to fully leverage the architectural features that C6000™ processors offer code optimization may be required. First this document reviews five key concepts in understanding the C6000 DSP architecture and optimization. Then
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Manufacturer's Classification
- Semiconductors> Processors> Digital Signal Processors> C6000 DSP> Other C6000 DSP