Fixed-Point Digital Signal Processor
PDF, 85 Kb, Revision: A, File published: Nov 28, 2007
This application report discusses the power consumption of the Texas Instruments TMS320TCI6482 digital signal processor (DSP). The power consumption on the TCI6482 device is highly application-dependent; therefore, a power spreadsheet that predicts power consumption is provided along with this document. The power spreadsheet can be used for the purpose of modeling power consumption for user applic
PDF, 404 Kb, File published: Nov 1, 2009
This application note describes how to create a DSP boot image from a COFF file (.out file), which can be used for host boot, such as HPI/PCI boot, RapidIO boot, etc. The implementation of the DSP Boot Assist Tool is introduced and sample source code is provided with this application note.
PDF, 219 Kb, File published: Nov 1, 2009
The TMS320TCI6842 integrates an EMAC module, which can be used to move data between the devices on the same Ethernet network. It supports 10/100/1000Mbps, and four types of interfaces to the physical layer device (PHY): MII, RMII, GMII and RGMII.This document provides EMAC bandwidth data measured under various operating conditions. The CPU load relevant to the Ethernet packet transfer is also
PDF, 195 Kb, File published: Nov 30, 2006
The enhanced DMA v3 (EDMA3) controller of the TMS320TCI6482 device is a highly efficient data transfer engine, capable of maintaining transfers at up to 21 GB/sec at a 1 GHz CPU clock frequency. This document details measured bandwidth achieved under various operating conditions. For more information on ideal transfer bandwidth and scheduling transfers, please consult TMS320TCI648x DSP Enhanced
PDF, 79 Kb, File published: Sep 5, 2006
This application report describes how to prepare a TCI648x application for the I2C boot load process.The enclosed .zip archive contains all utilities and examples necessary to build a test application, program it into DSKTCI6482's I2C ROM, change the boot mode to I2C boot load, and verify that the test application has been loaded from the I2C and is running correctly.
PDF, 161 Kb, File published: Nov 30, 2006
Viterbi decoder lies at the heart of all of the wireless standards. Viterbi coprocessors (VCP2) are programmable peripherals used to decode convolutional codes. It is integrated into Texas Instruments TMS320TCI648x digital signal processor (DSP). This application report gives the channel density for VCP2 under various conditions, the CPU load for pre-processing VCP2 input data is also provided.
PDF, 134 Kb, Revision: C, File published: May 13, 2010
This application report contains implementation instructions for the DDR2 interface contained on the TCI6482 DSP device. The approach to specifying interface timing for the DDR2 interface is quite different than on previous devices.The previous approach specified device timing in terms of data sheet specifications and simulation models. The customer was required to obtain compatible memory de
PDF, 210 Kb, File published: Dec 13, 2006
Turbo decoder lies at the heart of all of the third-generation (3G) wireless standards. The turbo coprocessors (TCP2) are programmable peripherals used to decode turbo codes. It is integrated into Texas Instruments TMS320TCI648x Digital Signal Processor (DSP). This application report gives the channel density data for TCP2 under various conditions, the CPU load for pre-processing TCP2 input data i
PDF, 128 Kb, Revision: A, File published: Aug 24, 2006
This application report contains implementation instructions for the Serial Rapid I/O (SRIO) interface on the TMS320TCI6482 DSP device. The approach to specifying interface timing and physical requirements for the SRIO interface is quite different than previous approaches for other interfaces.Serial Rapid I/O is an industry-standard high-speed switched-packet interconnect. Physical layer data
PDF, 3.2 Mb, Revision: B, File published: Apr 25, 2006
This document describes system design considerations for the TMS320TCI6482 (TCI6482). It also gives comparisons to designing with the TMS320TCI100 (TCI100) for those familiar with that device. The objective of this document is to cover system design considerations for the TCI6482. Those familiar with the TCI100 can use the comparisons to migrate a TCI100 design to the TCI6482. In some cases there
PDF, 345 Kb, File published: Dec 23, 2005
The TMS320TCI648x devices introduce a newly designed Enhanced Direct Memory Access (EDMA3). The EDMA3 has many new features that improve system performance and enhance debugging capabilities. This document summarizes the key differences between EDMA3 on the TMS320TCI648x devices and EDMA2 on the TMS320C64x devices. This document also provides guidance for migrating from EDMA2 to EDMA3.
PDF, 122 Kb, File published: Nov 16, 2004
The C64X+ Megamodule supports a wide variety of internal memory configurations by allowing the L1 program and data memory (L1P and L1D) to set as cache only, SRAM only, or a mixture of cache and SRAM. In addition, the C64x+ Megamodule provides new system functionality including: cache freeze, Internal DMA (IDMA), bandwidth management, and memory protection. This document discusses the enhancements
PDF,
293 Kb, File published:
Feb 11, 2011In most customer applications, a high level of decoding bit error rate (BER) performance is required. Since Convolutional codes and Turbo codes are widely used in wireless communication systems, TI DSPs integrate two high-performance embedded coprocessors (enhanced Viterbi decoder coprocessor and enhanced Turbo decoder coprocessor) that significantly speed up channel-decoding operations on-chip.
PDF, 80 Kb, Revision: A, File published: Jul 19, 2013
This application report describes the error detection and correction mechanism of the C64x+/C674x megamodule L1P and L2 memories implemented on some devices. Depending on the type of application, these mechanisms are used to either provide diagnostic measures to detect faults in the memory that could lead to unacceptable risk for the user or to increase the availability of the system.
PDF, 310 Kb, Revision: A, File published: Oct 20, 2005
This document describes migration from the Texas Instruments TMS320C64xв„ў digital signal processor (DSP) to the TMS320C64x+в„ў DSP. The objective of this document is to indicate differences between the two cores and to briefly describe new features. Functionality in the devices that is identical is not included. For detailed information about either device, see the TMS320C64x/C64x+ DSP
PDF, 125 Kb, File published: Apr 15, 2009
Model Line
Series:
TMS320TCI6482 (4)
Manufacturer's Classification
- Semiconductors> Processors> Other Processors
