Datasheet Linear Technology LTC2274

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Design Notes

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  Maximize the Performance of 16-Bit, 105Msps ADC with Careful IF SIgnal Chain Design &mdash DN468
  PDF, 93 Kb, File published: May 30, 2009
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  Maximize the Performance of 16-Bit, 105Msps ADC with Careful
  IF Signal Chain Design
  Design Note 468
  Clarence Mayott and Derek Redmayne For instance, the LTC В®2274 provides excellent AC performance with an appropriate IF signal chain. The LTC2274
  is a 16-bit, 105Msps ADC that serially transmits 8B/10B
  encoded output data compliant with the JESD204 specification. It uses a single differential transmission line pair
  to reduce the number of IO lines required to transmit
  output data. The LTC2274 has 77dB of SNR, and 100dB
  of spurious free dynamic range.
  Signal Chain Topology
  Figure 2 details a signal chain optimized for a 70MHz
  center frequency and a 20MHz bandwidth driving the
  LTC2274. The п¬Ѓnal п¬Ѓlter and circuitry around the ADC
  are shown in detail. The earlier stages of the chain can
  be changed to suit a target application.
  The first stage of amplification in the chain uses an AH31
  from TriQuint Semiconductor. This GaAs FET amplifier offers a low noise figure and high IP3 point, which
  minimizes distortion caused by the amplifier stage. It
  provides 14dB of gain over a wide frequency region. The
  high IP3 prevents intermodulation distortion between
  frequencies outside the passband of the surface acoustic
  wave (SAW) п¬Ѓlter.
  A SAW п¬Ѓlter follows the ampliп¬Ѓcation stage for band …

Articles

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  Maximize the Performance of 16-Bit, 105Msps ADC with Careful IF Signal Chain Design &mdash LT Journal
  PDF, 273 Kb, File published: Dec 1, 2009
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  L DESIGN IDEAS Maximize the Performance of 16-Bit,
  105Msps ADC with Careful IF Signal
  Chain Design by Clarence Mayott and Derek Redmayne
  Introduction
  Modern communication systems
  require an ADC to receive an analog
  signal and then convert it into a digital
  signal that can be processed with an
  FPGA. The job of a mixed signal engineer is to optimize the signal at the
  input of the ADC to maximize overall system performance. This usually
  requires a signal chain comprised of
  multiple gain and filtering sections.
  An ADC is only as good as the signal
  it is measuring.
  For instance, the LTC2274 provides excellent AC performance with an appropriate IF signal chain. The
  LTC2274 is a 16-bit, 105Msps ADC
  that serially transmits 8B/10B encoded output data compliant with
  the JESD204 specification. It uses a
  single differential transmission line
  pair to reduce the number of IO lines 5.0V 5.0V L3
  180nH
  C32
  56pF L4 …

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  Serial Interface for High Speed Data Converters Simplifies Layout over Traditional Parallel Devices &mdash LT Journal
  PDF, 417 Kb, File published: Sep 23, 2008
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  DESIGN FEATURES L Serial Interface for High Speed Data
  Converters Simplifies Layout over
  Traditional Parallel Devices
  by Clarence Mayott Introduction Current Mode Logic and
  8B/10B Encoding Allows
  High Speed Serial Data
  Transfer AMPLITUDE (dBFS) The LTC2274 achieves excellent signal
  to noise ratio (SNR) performance of
  77.6dBFS and spurious free dynamic
  range (SFDR) of 100dB at baseband,
  as shown in Figure 1. The input topology of the LTC2274 family is based on
  its predecessor, the LTC2207 family,
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Manufacturer's Classification

• Data Conversion > Analog-to-Digital Converters (ADC) > High Speed ADCs (Fs >=10Msps)