Datasheet Linear Technology LTC3874IUFD#PBF

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Design Notes

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  VID Controller with Phase Extender Provides 120A Power Supply for Latest Generation of FPGAs, ASICs and Processors &mdash DN547
  PDF, 335 Kb, File published: Jan 12, 2016
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  VID Controller with Phase Extender Provides 120A Power
  Supply for Latest Generation of FPGAs, ASICs and Processors
  Design Note 547
  Mike Shriver
  Introduction
  The current drawn by FPGAs, ASICs and processors
  for high performance servers, network and computing
  systems continues to rise, and load currents of 100A
  or greater are becoming common. Meanwhile, the
  chip's operating voltages are dropping to 0.9V and
  below with tighter voltage regulation requirements.
  For many of these applications, the core voltage may
  need to be adjusted for optimum performance with
  a VID (voltage identification) interface. A significant
  challenge is clearly placed on the power supply
  designer to meet the demands of high efficiency and
  tight output voltage regulation with a small amount
  of board space.
  One way to meet these demands is to use the LTC3877
  and LTC3874 chipset. The LTC3877 is a peak current
  mode, VID-controlled dual output synchronous
  VIN
  6V TO …

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  Powering Altera Arria 10 FPGA and Arria 10 SoC: Tested and Verified Power Management Solutions &mdash DN549
  PDF, 1.6 Mb, File published: Feb 19, 2016
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  Powering Altera ArriaВ 10 FPGA andВ Arria 10 SoC: Tested
  and Verified Power Management Solutions
  Design Note 549
  Afshin Odabaee
  Introduction
  FPGA development kits allow system developers to
  evaluate an FPGA without having to design a complete
  system. Figures 1 and 2 show Altera’s new 20nm
  Arria 10 FPGAs and Arria 10В SoCs (System-on-Chip)
  development boards. These boards are tested and
  verified by Altera, exemplifying best design practices
  in layout, signal integrity and power management.
  Power Management for Core, System and I/O
  The power management solution for high end FPGAs,
  including the Arria 10, should be carefully selected.
  A well thought-out power management design can
  reduce PCB size, weight and complexity, as well as
  lower power consumption and cooling costs. And it
  is essential to achieve optimal system performance.
  ForВ example, the 0.95V at 105A supplied by the 12V
  DC/DC regulator powering the core of the Arria 10 GX
  FPGA in Figure 1 has several features that complement
  the power saving schemes of the SoC: Figure 1. Arria 10 GX FPGA Development Kit …

Articles

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  4-Phase Power Supply Delivers 120A in Tiny Footprint, Features Ultralow DCR Sensing for High Efficiency &mdash LT Journal
  PDF, 313 Kb, File published: Jul 7, 2015
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  4-Phase Power Supply Delivers 120A in Tiny Footprint,
  Features Ultralow DCR Sensing for High Efficiency
  Yingyi Yan, Haoran Wu and Jian Li The LTC3875 is a feature-rich dual-output synchronous
  buck controller that meets the power density demands
  of modern high speed, high capacity data processing
  systems, telecom systems, industrial equipment and DC
  power distribution systems. The LTC3875 delivers high
  efficiency with reliable current mode control, ultralow DCR
  sensing and strong integrated drivers in a 6mm Г— 6mm
  40-pin QFN. Multiple LTC3875s can be paralleled to provide
  higher current, or it can be combined with the LTC3874
  to deliver the same performance with a smaller footprint.
  The LTC3874 is a small footprint
  (4mm Г— 5mm QFN), dual PolyPhaseВ® current mode synchronous step-down slave
  controller (phase extender). It is suitable
  for high current, multiphase applications
  when paired with a companion master
  controller, such as LTC3875. The LTC3874
  can use sub-milliohm DC resistance
  power inductors to optimize efficiency.
  Immediate response to system faults
  guarantees reliability of the total solution. 1V V OUT, 120A CONVERTER WITH
  PARALLEL LTC3875s The LTC3875 can be easily configured as …

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  Avoid Debugging Cycles in Power Management for FPGA, GPU and ASIC Systems &mdash LT Journal
  PDF, 3.2 Mb, File published: Aug 25, 2016
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  Avoid Debugging Cycles in Power Management for FPGA,
  GPU and ASIC Systems
  Afshin Odabaee When it comes to designing FPGA, GPU or ASIC controlled systems, the number of
  design challenges related to power management and analog systems pale in comparison
  to those related to digital design. Nevertheless, it is risky to assume that power system
  design can be left to “later,” or taken in line with digital design. Even seemingly innocuous
  problems in power supply design can significantly delay the release of a system, as any
  added time to the power system debugging cycle can halt all work on the digital side.
  A good way to put DC/DC regulation
  issues to rest is to use a verified development kit offered by the FPGA, GPU or
  ASIC vendor. Often, the design itself or
  a similar design is available as a board/
  kit by the suppliers of power products
  and FPGA, GPU and ASIC manufacturers. Using a tested and verified kit unburdens
  system designers of most power system
  and analog issues, allowing them instead
  to focus their energies on configuring the
  complex digital systems. The optimum
  power system layout is taken care of
  before significant design is undertaken. THOUGHTFUL POWER MANAGEMENT
  IS CHALLENGING AT THE START Every design task is initially daunting,
  and power management design is no
  exception. This is the case when power is …

Model Line

Manufacturer's Classification

• Power Management > Switching Regulator > Step-Down (Buck) Regulators > High Input Voltage Buck | External Power Switch Buck Controllers
• Space & Harsh Environment > Extended Temperature Plastic (H & MP) > Extended Temperature (H & MP) Switching Regulators

Other Names:

LTC3874IUFDPBF, LTC3874IUFD PBF