Datasheet Linear Technology LTM4632IY

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Design Notes

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  Ultrathin Triple Output ОјModule Regulator for DDR, QDR and QDR-IV SRAM Fits 0.5cm2 Area and Backside of PCB &mdash DN551
  PDF, 340 Kb, File published: Apr 15, 2016
  Extract from the document

  Ultrathin Triple Output ВµModule Regulator for DDR, QDR
  and QDR-IV SRAM Fits 0.5cm2 Area and Backside of PCB
  Design Note 551
  Sam Young and Afshin Odabaee
  Introduction
  Delivering the highest RTR (random transaction rate)
  of QDR (quad data rate) SRAMs, QDR-IV provides up to
  400Gbps data transfer for high bandwidth networking,
  high performance computing and intensive data
  processing applications. A key challenge at these
  faster data rates is maintaining the integrity of the
  data transferred between the SRAM and devices such
  as high speed FPGAs and processors.
  A good solution is to place the SRAM—QDR-IV, QDR
  or DDR, for example—very close to the interfaced
  devices on the PCB’s topside. To conserve PCB area
  and minimize induced PCB parasitic noise on data
  bus lines, the DC/DC regulator circuit powering the
  QDR-IV SRAM data bus drivers should be placed
  nearby. The challenge is finding space for regulators
  on a densely populated PCB.
  Using a complete DC/DC regulator with onboard
  inductor and MOSFETs housed in a compact package …

Articles

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  Ultrathin Triple Output µModule Regulator for DDR, QDR and QDR-IV SRAM Fits 0.5cm2 Area and Backside of PCB &mdash LT Journal
  PDF, 287 Kb, File published: Aug 11, 2016
  Extract from the document

  Ultrathin Triple Output ВµModule Regulator for DDR, QDR and
  QDR-IV SRAM Fits 0.5cm2 Area and Backside of PCB
  Sam Young and Afshin Odabaee Delivering the highest RTR (random transaction rate) of QDR (quad data rate) SRAMs,
  QDR-IV provides up to 400Gbps data transfer for high bandwidth networking,
  high performance computing and intensive data processing applications. A key
  challenge at these faster data rates is maintaining the integrity of the data transferred
  between the SRAM and devices such as high speed FPGAs and processors.
  A good solution is to place the SRAM—
  QDR-IV, QDR or DDR, for example—very
  close to the interfaced devices on the
  PCB’s topside. To conserve PCB area and
  minimize induced PCB parasitic noise
  on data bus lines, the DC/DC regulator
  circuit powering the QDR-IV SRAM data
  bus drivers should be placed nearby.
  The challenge is finding space for regulators on a densely populated PCB. Figure 1. Typical LTM4632
  DDR3 application VIN
  3.6V TO
  15V Using a complete DC/DC regulator with
  onboard inductor and MOSFETs housed in
  a compact package is one solution. But the
  scarcity of area on the top of the PCB can
  render even compact solutions insufficient. …

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Manufacturer's Classification

• Power Management > Switching Regulator > DDR Memory/Bus Termination
• µModule Solutions > µModule Regulators > µModule Buck Regulators