DATASHEET
KAD5512HP FN6808
Rev 4.00
May 31, 2016 High Performance 12-Bit, 250/210/170/125MSPS ADC Features The KAD5512HP is the high performance member of the
KAD5512 family of 12-bit analog-to-digital converters. Designed
with Intersil’s proprietary FemtoCharge™ technology on a
standard CMOS process, the family supports sampling rates of
up to 250MSPS. The KAD5512HP is part of a pin-compatible
portfolio of 10, 12 and 14-bit A/Ds with sample rates ranging
from 125MSPS to 500MSPS. Pin-compatible with the KAD5512P Family, offering 2.2dB
higher SNR Programmable gain, offset and skew control 950MHz analog input bandwidth 60fs Clock jitter A Serial Peripheral Interface (SPI) port allows for extensive
configurability, as well as fine control of various parameters
such as gain and offset. Over-range indicator Selectable clock divider: Г 1, Г 2 or Г 4 Digital output data is presented in selectable LVDS or CMOS
formats. The KAD5512HP is available in 72 and 48 Ld QFN
packages with an exposed paddle. Operating from a 1.8V
supply, performance is specified across the full industrial
temperature range (-40°C to +85°C). Clock phase selection Key Specifications Programmable built-in test patterns SNR = 68.2dBFS for fIN = 105MHz (-1dBFS) Pb-free (RoHS compliant) SFDR = 81.1dBc for fIN = 105MHz (-1dBFS) Applications Nap and sleep modes Two’s complement, gray code or binary data format DDR LVDS-compatible or LVCMOS outputs Single-supply 1.8V operation Power Consumption
-429/345mW at 250/125MSPS (SDR Mode)
-390/309mW at 250/125MSPS (DDR Mode) Power Amplifier linearization Radar and satellite antenna array processing Broadband communications High-performance data acquisition Communications test equipment CLKP OVDD AVDD CLKDIV WiMAX and microwave receivers CLKOUTP CLOCK
GENERATION CLKN CLKOUTN D[11:0]P
12-BIT
250 MSPS
ADC VINN …
