HMC987LP5E
v03.1112 Clock Distribution -SMT LOW NOISE 1:9 FANOUT BUFFER
DC -8 GHz
Typical Applications Features The is suitable for: Ultra Low Noise Floor: -166 dBc/Hz @ 2 GHz • SONET, Fibre Channel, GigE Clock Distribution
• ADC/DAC Clock Distribution
• Low Skew and Jitter Clock or Data Fanout
• Wireless/Wired Communications
• Level Translation
• High Performance Instrumentation
• Medical Imaging
• Single-Ended to Differential Conversion Wideband: DC -8 GHz Operating Frequency
Flexible Input Interface:
LVPECL, LVDS, CML, CMOS Compatible
AC or DC Coupling
On-Chip Termination 50 or 150 Ω (100/300 Ω Diff.)
Multiple Output Drivers:
Up to 8 Differential or 16 Single-Ended LVPECL
Outputs:
800 mVpp into 50 Ω Single-Ended (+3 dBm Fo)
One Adjustable Power CML/RF Output:
-9 to 3 dBm Single-Ended
Serial or Parallel Control, Hardware Chip-Enable
Power-Down Current < 1 uA …
